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Control Registers
1579
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.30 Transfer Group Interrupt Level Clear Register (TGITLVCR)
The register TGITLVCR clears the level of interrupts for transfer completed interrupt and for transfer
suspended interrupt to level 0.
The register map shown in Figure 28-65 and Table 28-39 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 28-65. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]
31 16
CLRINTLVLRDY[15:0]
R/W-0
15 0
CLRINTLVLSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 28-39. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions
Bit Field Value Description
31-16 CLRINTLVLRDY[n] Transfer-group completed interrupt level clear. Bit 16 corresponds to TG0, bit 17 corresponds to
TG1, and so on.
0 Read: The TGx-completed interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1 Read: The TGx-completed interrupt is set to INT1.
Write: Clear the TGx-completed interrupt to INT0.
15-0 CLRINTLVLSUS[n] Transfer group suspended interrupt level clear. Bit 0 corresponds to TG0, bit 1 corresponds to
TG1, and so on.
0 Read: TGx-suspended interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1 Read: The TGx-suspended interrupt is set to INT1.
Write: Clear the TG-x suspended interrupt to INT0.
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