www.ti.com
SCI/LIN Control Registers
1681
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7.6 SCI Set Interrupt Level Register (SCISETINTLVL)
Figure 29-33 and Table 29-18 illustrate this register.
Figure 29-33. SCI Set Interrupt Level Register (SCISETINTLVL) (offset = 14h)
31 30 29 28 27 26 25 24
SET BE
INT LVL
SET PBE
INT LVL
SET CE
INT LVL
SET ISFE
INT LVL
SET NRE
INT LVL
SET FE
INT LVL
SET OE
INT LVL
SET PE
INT LVL
R/WL-0 R/WL-0 R/WL-0 R/WL-0 R/WL-0 R/W-0 R/W-0 R/W-0
23 19 18 17 16
Reserved
SET RX DMA
ALL INT LVL
Reserved
R-0 R/WC-0 R-0
15 14 13 12 10 9 8
Reserved
SET ID
INT LVL
Reserved
SET RX
INT LVL
SET TX
INT LVL
R-0 R/WL-0 R-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SET
TOA3WUS
INT LVL
SET TOAWUS
INT LVL
Reserved
SET TIMEOUT
INT LVL
Reserved
SET WAKEUP
INT LVL
SET BRKDT
INT LVL
R/WL-0 R/WL-0 R-0 R/WL-0 R-0 R/W-0 R/WC-0
LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset
Table 29-18. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions
Bit Field Value Description
31 SET BE INT LVL Set bit error interrupt level. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
30 SET PBE INT LVL Set physical bus error interrupt level. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
29 SET CE INT LVL Set checksum-error interrupt level. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
28 SET ISFE INT LVL Set inconsistent-synch-field-error interrupt level. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
27 SET NRE INT LVL Set no-response-error interrupt level. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
26 SET FE INT LVL Set framing-error interrupt level. This bit is effective in LIN or SCI-compatible mode.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
To Next Page
Loading...
Need help?
General
