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SPNU563A–March 2018
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EMAC/MDIO Module
32.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN)
The EMAC control module miscellaneous interrupt enable register (C0MISCEN) is shown in Figure 32-21
and described in Table 32-17
Figure 32-21. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN)
(offset = 1Ch)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved STATPENDEN HOSTPENDEN LINKINT0EN USERINT0EN
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32-17. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN)
Bit Field Value Description
31-4 Reserved 0 Reserved
3 STATPENDEN Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated.
0 C0MISCPULSE generation is disabled for EMAC STATPEND interrupts.
1 C0MISCPULSE generation is enabled for EMAC STATPEND interrupts.
2 HOSTPENDEN Enable C0MISCPULSE interrupt generation when EMAC host interrupts are generated.
0 C0MISCPULSE generation is disabled for EMAC HOSTPEND interrupts.
1 C0MISCPULSE generation is enabled for EMAC HOSTPEND interrupts.
1 LINKINT0EN Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to
USERPHYSEL0) are generated.
0 C0MISCPULSE generation is disabled for MDIO LINKINT0 interrupts.
1 C0MISCPULSE generation is enabled for MDIO LINKINT0 interrupts.
0 USERINT0EN Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding
to USERACCESS0) are generated.
0 C0MISCPULSE generation is disabled for MDIO USERINT0.
1 C0MISCPULSE generation is enabled for MDIO USERINT0.