Texas Instruments TMS570LC4357 - Page 1861

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SPNU563A–March 2018
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EMAC/MDIO Module
32.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers
(C0RXTHRESHSTAT)
The EMAC control module receive threshold interrupt status register (C0RXTHRESHSTAT) is shown in
Figure 32-22 and described in Table 32-18
Figure 32-22. EMAC Control Module Receive Threshold Interrupt Status Register
(C0RXTHRESHSTAT) (offset = 40h)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RXCH7THRESH
STAT
RXCH6THRESH
STAT
RXCH5THRESH
STAT
RXCH4THRESH
STAT
RXCH3THRESH
STAT
RXCH2THRESH
STAT
RXCH1THRESH
STAT
RXCH0THRESH
STAT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 32-18. EMAC Control Module Receive Threshold Interrupt Status Register
(C0RXTHRESHSTAT)
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RXCH7THRESHSTAT Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register.
0 RX Channel 7 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 7 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
6 RXCH6THRESHSTAT Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register.
0 RX Channel 6 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 6 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register.
0 RX Channel 5 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 5 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
4 RXCH4THRESHSTAT Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register.
0 RX Channel 4 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 4 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
3 RXCH3THRESHSTAT Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register.
0 RX Channel 3 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 3 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
2 RXCH2THRESHSTAT Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register.
0 RX Channel 2 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 2 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
1 RXCH1THRESHSTAT Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register.
0 RX Channel 1 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 1 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.
0 RXCH0THRESHSTAT Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register.
0 RX Channel 0 does not satisfy conditions to generate a C0RXTHRESHPULSE interrupt.
1 RX Channel 0 satisfies conditions to generate a C0RXTHRESHPULSE interrupt.