Texas Instruments TMS570LC4357

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SPNU563A–March 2018
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eFuse Controller
38.4 eFuse Controller Registers
All registers in the eFuse Controller module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are
allowed. Table 38-2 provides a quick reference to each of these registers. Specific bit descriptions are
discussed in the following subsections. The base address for the control registers is FFF8 C000h.
Table 38-2. eFuse Controller Registers
Offset Acronym Register Description Section
1Ch EFCBOUND EFC Boundary Control Register Section 38.4.1
2Ch EFCPINS EFC Pins Register Section 38.4.2
3Ch EFCERRSTAT EFC Error Status Register Section 38.4.3
48h EFCSTCY EFC Self Test Cycles Register Section 38.4.4
4Ch EFCSTSIG EFC Self Test Signature Register Section 38.4.5
38.4.1 EFC Boundary Control Register (EFCBOUND)
Figure 38-2 and Table 38-3 describe the EFCBOUND register. The eFuse Boundary Control Register is
used to test the connections between the eFuse controller and the ESM module. The eFuse Boundary
Control Register is also used to initiate an eFuse controller ECC self-test.
Figure 38-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch]
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
Reserved EFC Self Test
Error
EFC Single Bit
Error
EFC Instruction
Error
EFC Autoload
Error
Self Test
Error OE
Single Bit
Error OE
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 8
Instruction
Error OE
Autoload
Error OE
EFC ECC Selftest
Enable
Reserved
R/W-0 R/W-0 R/W-0 R-0
7 4 3 0
Reserved Input Enable
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)
Table 38-3. EFC Boundary Register (EFCBOUND) Field Descriptions
Bit Field Value Description
31-22 Reserved 0 Read returns 0. Writes have no effect.
21 EFC Self Test Error This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. This signal
is attached to ESM error Group 1, Channel 41.
0 Drives the self test error signal low, if Self Test OE is high.
1 Drives the self test error signal high, if Self Test OE is high.
20 EFC Single Bit Error This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. This signal
is attached to ESM error Group 1, Channel 40.
0 Drives the self test error signal low, if Single Bit Error OE is high.
1 Drives the self test error signal high, if Single Bit Error OE is high.