Texas Instruments TMS570LC4357 - Page 40

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40
SPNU563A–March 2018
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List of Figures
15-6. Clock0 Not Present - Results in an Error and Stops Counting ..................................................... 547
15-7. DCC Global Control Register (DCCGCTRL) [offset = 00] .......................................................... 550
15-8. DCC Revision Id Register (DCCREV) [offset = 4h] ................................................................. 551
15-9. DCC Counter0 Seed Register (DCCCNT0SEED) [offset = 8h] .................................................... 551
15-10. DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch] ..................................................... 552
15-11. DCC Counter1 Seed Register (DCCCNT1SEED) [offset = 10h] .................................................. 552
15-12. DCC Status Register (DCCSTAT) [offset = 14h] .................................................................... 553
15-13. DCC Counter0 Value Register (DCCCNT0) [offset = 18h] ......................................................... 554
15-14. DCC Valid0 Value Register (DCCVALID0) [offset = 1Ch] .......................................................... 555
15-15. DCC Counter1 Value Register (DCCCNT1) [offset = 20h] ......................................................... 555
15-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h] ......................... 556
15-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 28h] ......................... 557
16-1. Block Diagram............................................................................................................. 559
16-2. Interrupt Response Handling............................................................................................ 560
16-3. ERROR Pin Response Handling ....................................................................................... 560
16-4. ERROR Pin Timing - Example 1........................................................................................ 562
16-5. ERROR Pin Timing - Example 2........................................................................................ 562
16-6. ERROR Pin Timing - Example 3........................................................................................ 562
16-7. ERROR Pin Timing - Example 4........................................................................................ 563
16-8. ERROR Pin Timing - Example 5........................................................................................ 563
16-9. ERROR Pin Timing - Example 6........................................................................................ 563
16-10. ESM Initialization.......................................................................................................... 564
16-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [offset = 00h] ........................ 566
16-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) [offset = 04h] ....................... 566
16-13. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) [offset = 08h] ......................................... 567
16-14. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) [offset = 0Ch] ...................................... 567
16-15. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) [offset = 10h] ........................................... 568
16-16. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) [offset = 14h]......................................... 568
16-17. ESM Status Register 1 (ESMSR1) [offset = 18h] .................................................................... 569
16-18. ESM Status Register 2 (ESMSR2) [offset = 1Ch] .................................................................... 569
16-19. ESM Status Register 3 (ESMSR3) [offset = 20h] .................................................................... 570
16-20. ESM ERROR Pin Status Register (ESMEPSR) [offset = 24h] ..................................................... 570
16-21. ESM Interrupt Offset High Register (ESMIOFFHR) [offset = 28h] ................................................. 571
16-22. ESM Interrupt Offset Low Register (ESMIOFFLR) [offset = 2Ch].................................................. 572
16-23. ESM Low-Time Counter Register (ESMLTCR) [offset = 30h] ...................................................... 573
16-24. ESM Low-Time Counter Preload Register (ESMLTCPR) [offset = 34h]........................................... 573
16-25. ESM Error Key Register (ESMEKR) [offset = 38h]................................................................... 574
16-26. ESM Status Shadow Register 2 (ESMSSR2) [offset = 3Ch]........................................................ 574
16-27. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) [offset = 40h] ................................ 575
16-28. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) [offset = 44h].............................. 575
16-29. ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) [offset = 48h] ......................................... 576
16-30. ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) [offset = 4Ch] ...................................... 576
16-31. ESM Interrupt Level Set/Status Register 4 (ESMILSR4) [offset = 50h] ........................................... 577
16-32. ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) [offset = 54h]......................................... 577
16-33. ESM Status Register 4 (ESMSR4) [offset = 58h] .................................................................... 578
16-34. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) [offset = 80h] ................................ 579
16-35. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) [offset = 84h].............................. 579
16-36. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) [offset = 88h] ......................................... 580
16-37. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) [offset = 8Ch] ...................................... 580