Texas Instruments TMS570LC4357 - Page 39

www.ti.com
39
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
List of Figures
11-8. MPU Error Status Register (MPUERRSTAT) [offset = 10h] ........................................................ 474
11-9. MPU Error Address Register (MPUERRADDR) [offset = 14h] ..................................................... 476
11-10. MPU Control Register 1 (MPUCTRL1) [offset = 20h]................................................................ 476
11-11. MPU Control Register 2 (MPUCTRL2) [offset = 24h]................................................................ 477
11-12. MPU Type Register (MPUTYPE) [offset = 2Ch]...................................................................... 478
11-13. MPU Region Base Address Register (MPUREGBASE) [offset = 30h] ............................................ 479
11-14. MPU Region Size and Enable Register (MPUREGSENA) [offset = 34h] ......................................... 479
11-15. MPU Region Access Control Register (MPUREGACR) [offset = 38h] ............................................ 481
11-16. MPU Region Number Register (MPUREGNUM) [offset = 3Ch] .................................................... 482
12-1. EPC System Block Diagram............................................................................................. 485
12-2. EPC REVID Register (EPCREVID) (offset = 00h).................................................................... 489
12-3. EPC Control Register (EPCCNTRL) (offset = 04h) .................................................................. 490
12-4. Uncorrectable Error Status Register (UERRSTAT) (offset = 08h) ................................................. 491
12-5. EPC Error Status Register (EPCERRSTAT) (offset = 0Ch)......................................................... 492
12-6. FIFO Full Status Register (FIFOFULLSTAT) (offset = 10h)......................................................... 493
12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) (offset = 14h)..................................... 494
12-8. CAM Index Available Status Register (CAMAVAILSTAT) (offset = 18h).......................................... 494
12-9. Uncorrectable Error Address Register n (UERR_ADDR) (offset = 20h-24h) ..................................... 495
12-10. CAM Content Update Register n (CAM_CONTENT) (offset = A0h-11Ch)........................................ 495
12-11. CAM Index Registers (CAM_INDEXn) (offset = 200h-21Ch) ....................................................... 496
13-1. Block Diagram............................................................................................................. 499
13-2. CPU Input Inversion Scheme ........................................................................................... 504
13-3. CCM-R5F Status Register 1 (CCMSR1) (Offset = 00h) ............................................................. 508
13-4. CCM-R5F Key Register 1 (CCMKEYR1) (Offset = 04h) ............................................................ 509
13-5. CCM-R5F Status Register 2 (CCMSR2) (Offset = 08h) ............................................................. 510
13-6. CCM-R5F Key Register 2 (CCMKEYR2) (Offset = 0Ch)............................................................ 511
13-7. CCM-R5F Status Register 3 (CCMSR3) (Offset = 10h) ............................................................. 512
13-8. CCM-R5F Key Register 3 (CCMKEYR3) (Offset = 14h) ............................................................ 513
13-9. CCM-R5F Polarity Control Register (CCMPOLCNTRL) (Offset = 18h) ........................................... 513
13-10. CCM-R5F Status Register 4 (CCMSR4) (Offset = 1Ch)............................................................. 514
13-11. CCM-R5F Key Register 4 (CCMKEYR4) (Offset = 20h) ............................................................ 515
13-12. CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) (Offset = 24h).................................... 516
14-1. Clock Path from Oscillator through PLL to Device ................................................................... 519
14-2. Clock Generation Path ................................................................................................... 520
14-3. Oscillator Implementation................................................................................................ 521
14-4. Operation of the FM-PLL Module....................................................................................... 525
14-5. PLL Slip Detection and Reset/Bypass Block Diagram............................................................... 531
14-6. SSW PLL BIST Control Register 1 (SSWPLL1) [offset = 24h] ..................................................... 535
14-7. SSW PLL BIST Control Register 2 (SSWPLL2) [offset = 28h] ..................................................... 536
14-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = 2Ch]..................................................... 537
14-9. Basic PLL Circuit.......................................................................................................... 538
14-10. PFD Timing ................................................................................................................ 538
14-11. PLL Modulation Block Diagram ......................................................................................... 539
14-12. Frequency versus Time .................................................................................................. 540
15-1. DCC Operation............................................................................................................ 543
15-2. Counter Relationship ..................................................................................................... 545
15-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting ........................................... 545
15-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................ 546
15-5. Clock1 Not Present - Results in an Error and Stops Counting ..................................................... 546