Infineon Technologies TC1796 - Page 2128

User’s Manual L-12 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Registers 17-16 [1]
OCDS level 1 17-4 [1]
Debug actions 17-7 [1]
Debug event generation 17-6 [1]
of BCU 17-9 [1]
of CPU 17-4 [1]
of DMA 17-9 [1]
of PCP 17-8 [1]
Registers 17-8 [1]
OCDS level 2 17-10 [1]
Concurrent debugging 17-11 [1]
CPU trace 17-10 [1]
DMA trace 17-10 [1]
OCDS level 3 17-1 [1]
Overview 17-1 [1]
System block diagram 17-2 [1]
On-chip debug support
Registers
TR0EVT 2-18 [1]
TR1EVT 2-18 [1]
P
Pad test mode 5-50 [1]
Block diagram 5-50 [1]
Enable control 5-51 [1]
Registers 5-51 [1]
SCU_PTCON 5-52 [1]
SCU_PTDAT0 5-53 [1]
SCU_PTDAT1 5-54 [1]
SCU_PTDAT2 5-55 [1]
SCU_PTDAT3 5-56 [1]
Parity protection
General control 5-37 [1]
in CAN memories 22-213 [2]
in DMI memories 2-33 [1]
in DMU memories 8-3 [1]
in PCP memories 11-125 [1]
in PMI memories 2-25 [1]
PCP 11-1 [1]
Accessing from FPI bus 11-48 [1]
Architecture 11-2 [1]
Channel programs 11-25 [1]
Context models 11-11 [1]
Control and interrupt registers
11-52 [1]
Debugging 11-50 [1]
Error handling 11-38 [1]
General purpose registers 11-6 [1]
Implementation in TC1796 11-125 [1]
Instruction set details 11-72 [1]
Instruction set overview 11-40 [1]
Instruction timing 11-108 [1]
Interrupt operation 11-32 [1]
Overview 11-1 [1]
Programming 11-112 [1]
Programming model 11-6 [1]
Programming tips 11-118 [1]
Registers
ID 11-54 [1]
Overview 11-52 [1]
PCP_CLC 11-55 [1]
PCP_CS 11-56 [1]
PCP_ES 11-59 [1]
PCP_ICON 11-64 [1]
PCP_ICR 11-61 [1]
PCP_ITR 11-63 [1]
PCP_SRC0 11-67 [1]
PCP_SRC1 11-67 [1]
PCP_SRC10 11-70 [1]
PCP_SRC11 11-70 [1]
PCP_SRC2 11-68 [1]
PCP_SRC3 11-68 [1]
PCP_SRC4 11-69 [1]
PCP_SRC5 11-69 [1]
PCP_SRC6 11-69 [1]
PCP_SRC7 11-69 [1]
PCP_SRC8 11-69 [1]
PCP_SRC9 11-70 [1]
PCP_SSR 11-66 [1]
Peripheral control processor, see PCP
Pin configuration 1-35 [1]
Pin definitions and functions 1-34 [1]–??
PLL 3-10 [1]
Lock detection 3-19 [1]
Loss-of-lock recovery 3-19 [1]
Parameters 3-12 [1]