Infineon Technologies TC1796 - Page 2127

User’s Manual L-11 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Read frame 23-33 [2]
Write frame 23-28 [2]
Transmitter
Description of frame transmission
23-26 [2]
I/O line control 23-51 [2]
Typical application 23-2 [2]
Module clock generation 3-23 [1]
MSC
Applications 21-2 [2]
Downstream channel 21-5 [2]
Baud rate 21-20 [2]
Block diagram 21-5 [2]
Command frames 21-7 [2]
Data frames 21-9 [2]
Data repetition mode 21-15 [2]
Downstream counter 21-19 [2]
Frame formats 21-6 [2]
Output control 21-27 [2]
Passive time frames 21-11 [2]
Shift register operation 21-12 [2]
Transmission mode 21-14 [2]
Triggered mode 21-14 [2]
Features 21-4 [2]
I/O control 21-27 [2]
Interrupts 21-31 [2]
Command frame interrupt 21-32 [2]
Data frame interrupt 21-32 [2]
Interrupt request compressor
21-35 [2]
Receive data interrupt 21-34 [2]
Time frame finished interrupt
21-33 [2]
Kernel block diagram 1-19 [1], 21-3 [2]
Module implementation
Input/output function selection
21-70 [2]
Module clock control 21-65 [2]
Pad output driver characteristics
selection 21-74 [2]
Overview 21-3 [2]
Registers
DC 21-59 [2]
DD 21-59 [2]
DSC 21-41 [2]
DSDSH 21-47 [2]
DSDSL 21-46 [2]
DSS 21-44 [2]
ESR 21-48 [2]
ICR 21-49 [2]
ID 21-38 [2]
ISC 21-54 [2]
ISR 21-52 [2]
OCR 21-56 [2]
Offset addresses 21-36 [2]
Overview 21-36 [2]
UDx 21-60 [2]
USR 21-39 [2]
Upstream channel 21-21 [2]
Baud rate 21-25 [2]
Block diagram 21-21 [2]
Data frame protocol 21-22 [2]
Data reception 21-23 [2], 21-24 [2]
Input control 21-30 [2]
Parity checking 21-22 [2]
Sampling 21-26 [2]
N
NMI 14-25 [1]
NMI input 14-25 [1]
PLL NMI 14-25 [1]
SRAM parity error control 5-37 [1]
Status register NMISR 14-27 [1]
Watchdog timer NMI 14-25 [1]
O
OCDS
Cerberus 17-12 [1]
Communication mode 17-13 [1]
Features 17-12 [1]
Multi-core break switch 17-13 [1]
Registers 17-16 [1]
RW mode 17-12 [1]
Triggered transfers 17-13 [1]
Components 17-2 [1]
JTAG interface 17-15 [1]