Infineon Technologies TC1796 - Page 2126

User’s Manual L-10 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
SRSS3 24-214 [2]
LVDS outputs 10-85 [1]
M
Memory checker 12-110 [1]
Functionality 12-110 [1]
Registers 12-111 [1]
ID 12-112 [1]
IR 12-113 [1]
Offset addresses 12-111 [1]
Overview 12-111 [1]
RR 12-113 [1]
WR 12-114 [1]
Memory maps 9-1 [1]
Access restrictions 9-22 [1]
from DLMB 9-19 [1]
from PLMB 9-15 [1]
Segment 0 to 14 from SPB and RPB
9-6 [1]
Segment 15 from SPB and RPB
9-10 [1]
Segment contents 9-4 [1]
Memory protection system
Registers
Offset addresses 2-21 [1]
MLI
Access protection 23-47 [2]
Block diagram 1-25 [1], 23-49 [2]
Communication principles 23-6 [2]
Frames 23-10 [2]
Answer frame 23-18 [2]
Command frame 23-17 [2]
Copy base address frame 23-12 [2]
Layout 23-11 [2]
Optimized read frame 23-16 [2]
Optimized write frame 23-14 [2]
Write offset and data frame
23-13 [2]
Handshake signalling 23-19 [2]
Interrupts 23-55 [2]
Receiver interrupts 23-60 [2]
Transmitter interrupts 23-57 [2]
Kernel registers 23-75 [2]
Module implementation 23-124 [2]
Access protection 23-141 [2]
Clock generation 23-128 [2]
Input/output function selection
23-130 [2]
MLI0 block diagram 23-125 [2],
23-126 [2]
On-chip connections 23-139 [2]
Transfer window map 23-146 [2]
Naming conventions 23-3 [2]
Receiver
I/O line control 23-51 [2]
Registers
AER 23-88 [2]
ARR 23-89 [2]
FDR 23-79 [2]
Offset addresses 23-76 [2]
OICR 23-84 [2]
Overview 23-75 [2]
RDARR 23-116 [2]
RDATAR 23-114 [2]
RIER 23-117 [2]
RINPR 23-122 [2]
RISR 23-120 [2]
RPxBAR 23-115 [2]
RPxSTATR 23-113 [2]
SCR 23-78 [2], 23-81 [2], 23-83 [2]
TCBAR 23-104 [2], 23-110 [2]
TCMDR 23-97 [2]
TCR 23-90 [2]
TDRAR 23-101 [2]
TIER 23-105 [2]
TINPR 23-108 [2]
TISR 23-107 [2]
TPxAOFR 23-103 [2]
TPxBAR 23-102 [2]
TPxDATAR 23-101 [2]
TPxSTATR 23-95 [2]
TRSTATR 23-99 [2]
TSTATR 23-93 [2]
Transaction flow diagrams
Command frame 23-39 [2]
Copy base address 23-26 [2]