Infineon Technologies TC1796 - Page 2125

User’s Manual L-9 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
PLLCNT 24-167 [2]
PLLCTR 24-165 [2]
PLLDTR 24-168 [2]
PLLMTI 24-166 [2]
PLLREV 24-168 [2]
PLLSTP 24-167 [2]
SRNR 24-215 [2]
SRSC0 24-206 [2]
SRSC1 24-209 [2]
SRSC2 24-211 [2]
SRSC3 24-213 [2]
SRSS0 24-208 [2]
SRSS1 24-210 [2]
SRSS2 24-212 [2]
SRSS3 24-214 [2]
Signal generation unit (SGU)
Global timer cell 24-55 [2]
Global timers 24-37 [2]
Local timer cell 24-67 [2]
GPTA0
Registers
GTTIMk 24-171 [2]
I
Idle mode 5-5 [1]
Instruction timing 2-40 [1]–??
Interrupt system
Arbitration cycles 14-12 [1]
Arbitration process 14-12 [1]
Block diagram 14-2 [1]
Control register ICR 14-8 [1]
External interrupts 14-22 [1]
Hints for applications 14-18 [1]–
14-22 [1]
Interrupt control unit 14-8 [1]
Interrupt vector table 14-15 [1]
Overview 14-1 [1]
Priorities 14-19 [1]
Service request control register
14-3 [1], 14-4 [1]
Service request node table 14-23 [1]
Service request nodes 14-3 [1]
Service routine entering 14-13 [1]
Service routine exiting 14-14 [1]
Software initiated interrupts 14-22 [1]
Interrupts
Special system interrupts 5-35 [1]
External interrupts 5-36 [1]
Flash interrupt 5-36 [1]
FPU interrupt 5-35 [1]
L
LFI bridge 6-15 [1]
Address translation 6-15 [1]
Register
CON 6-17 [1]
Offset address 6-16 [1]
Overview 6-16 [1]
LMB 6-2 [1]
Basic operation 6-4 [1]
Default master 6-6 [1]
Features 6-2 [1]
Terms 6-2 [1]
Transaction types 6-3 [1]
LMI 8-8 [1]
Data read buffer 8-8 [1]
Local memory bus, see “LMB”
LTCA2
Registers
ID 24-235 [2]
LIMCRHg 24-245 [2]
LIMCRLg 24-243 [2]
LTCCTR63 24-188 [2]
LTCCTRk 24-180 [2]
LTCXR63 24-190 [2]
LTCXRk 24-190 [2]
MRACTL 24-236 [2]
MRADIN 24-238 [2]
MRADOUT 24-238 [2]
Offset addresses 24-233 [2]
OMCRHg 24-241 [2]
OMCRLg 24-239 [2]
Overview 24-233 [2]
SRSC2 24-211 [2]
SRSC3 24-213 [2]
SRSS2 24-212 [2]