Revision History
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SPNU563A–March 2018
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Revision History
• Figure 6-12: Updated Read/Write value of KICK0 bits to R/W-0 ................................................................ 330
• Figure 6-12: Changed LEGEND ..................................................................................................... 330
• Section 6.7.4: Added paragraph ..................................................................................................... 330
• Figure 6-13: Updated Read/Write value of KICK1 bits to R/W-0 ................................................................ 330
• Figure 6-13: Changed LEGEND ..................................................................................................... 330
• Chapter 7: F021 Level 2 Flash Module Controller (L2FMC) .................................................................. 338
• Table 7-1: Corrected for big endian.................................................................................................. 342
• Section 7.5.1: Changed sentence.................................................................................................... 345
• Figure 7-1: Changed figure ........................................................................................................... 345
• Figure 7-2: Added figure. Subsequent figures renumbered ...................................................................... 345
• Figure 7-7: Switched the order of the temperature sensor ADC reading and the temperature in the OTP ................ 348
• Figure 7-8: Switched the order of the temperature sensor ADC reading and the temperature in the OTP ................ 348
• Figure 7-9: Switched the order of the temperature sensor ADC reading and the temperature in the OTP ................ 348
• Table 7-8: Switched the order of the temperature sensor ADC reading and the temperature in the OTP................. 349
• Table 7-8: Changed Description of SxTEMP1, SxTEMP2, and SxTEMP3 fields.............................................. 349
• Section 7.5.2.6: Moved subsection into OTP Memory subsection. Subsequent subsections renumbered ................ 349
• Section 7.7.2: Updated second paragraph.......................................................................................... 350
• Section 7.7.2.1: Updated second paragraph ....................................................................................... 351
• Table 7-10: Deleted DIAG MODE 6 ................................................................................................. 352
• Table 7-10: Updated Name of test modes.......................................................................................... 352
• Table 7-12: Added Read Margin Control Register (FSPRD) ..................................................................... 355
• Section 7.10.2: Added subsection. Subsequent subsections, figures, and tables renumbered ............................. 357
• Figure 7-26: Changed default value of PSLEEP bit to C8h ...................................................................... 368
• Table 7-45: Updated Description of SECT_ERASED bit ......................................................................... 381
• Table 7-46: Updated Description of SECT_ERASED bit ......................................................................... 381
• Chapter 8: Level 2 RAM (L2RAMW) Module..................................................................................... 387
• Table 8-4: Corrected Description of DWDE bit to double-bit error............................................................... 395
• Table 8-8: Changed Description of TEST_MODE and TEST_ENABLE bits ................................................... 400
• Figure 8-8: Changed bits 15-0 to RAM_CHIP_SELECT.......................................................................... 401
• Chapter 9: Programmable Built-In Self-Test (PBIST) Module................................................................ 405
• Figure 9-2: Changed figure. Deleted FSRF1 ....................................................................................... 408
• Section 9.3.1: Changed code example.............................................................................................. 409
• Section 9.3.1: Changed step 6. Deleted ROM interface clock ................................................................... 409
• Section 9.3.1: Changed step 12. Deleted FSRF1 and ROM clock .............................................................. 409
• Section 9.3.1: Added last sentence with link to last paragraph .................................................................. 410
• Section 9.5: Changed second paragraph (write 1h) ............................................................................... 412
• Table 9-1: Deleted FSRF1 ............................................................................................................ 412
• Table 9-2: Added Note to RDS bit ................................................................................................... 413
• Section 9.5.3: Updated paragraph to remove bit [1]............................................................................... 415
• Section 9.5.3: Deleted PACT1 bullet ................................................................................................ 415
• Figure 9-5: Deleted bit [1] ............................................................................................................. 415
• Table 9-4: Deleted bit [1] .............................................................................................................. 415
• Section 9.5.6: Changed subsection title. Deleted FSRF1......................................................................... 418
• Section 9.5.6: Changed paragraph .................................................................................................. 418
• Section 9.5.6: Deleted Fail Status Fail Register 1 (FSRF1) figure. Subsequent figures renumbered ...................... 418
• Section 9.5.6: Deleted Fail Status Fail Register 1 (FSRF1) Field Descriptions table. Subsequent tables renumbered.. 418
• Section 9.6.1: Changed step 5. Deleted ROM interface clock ................................................................... 426
• Section 9.6.1: Changed step 12. Deleted FSRF1 and ROM clock .............................................................. 426
• Section 9.6.2: Changed step 5. Deleted ROM interface clock ................................................................... 427
• Section 9.6.2: Changed step 11. Deleted FSRF1 and ROM clock .............................................................. 427
• Chapter 10: Self-Test Controller (STC) Module................................................................................. 428
• Table 10-2: Changed format.......................................................................................................... 441
• Table 10-4: Changed format.......................................................................................................... 444
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