www.ti.com
Revision History
2199
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Revision History
• Table 10-6: Changed format.......................................................................................................... 444
• Table 10-9: Changed Description of RS_CNT bit. Added values 2h-3h ........................................................ 447
• Section 10.8.2: Added second sentence to NOTE ................................................................................ 448
• Chapter 11: System Memory Protection Unit (NMPU)......................................................................... 460
• Table 11-3: Deleted MPU Input Address Mask Register (MPUIAM) ............................................................ 471
• Figure 11-8: Updated Read/Write value of ERRFLAG bit to R/W1CP-0........................................................ 474
• Chapter 12: Error Profiling Controller (EPC).................................................................................... 483
• Figure 12-4: Updated Read/Write value of bits to R/W1CP-0.................................................................... 491
• Figure 12-5: Updated Read/Write value of bits to R/W1CP-0.................................................................... 492
• Figure 12-6: Updated Read/Write value of bits to R/W1CP-0.................................................................... 493
• Figure 12-7: Updated Read/Write value of bits to R/W1CP-0.................................................................... 494
• Chapter 13: CPU Compare Module for Cortex-R5F (CCM-R5F) ............................................................. 497
• Chapter 14: Oscillator and PLL .................................................................................................... 517
• Section 14.5: Updated third paragraph. Changed f
(HCLK)
to f
(GCLK)
................................................................. 525
• Table 14-1: Updated Frequency Limit value to f
(GCLK)
for f
PLL CLK
................................................................... 525
• Table 14-2: Updated formula for NF................................................................................................. 526
• Section 14.5.2.1: Changed table of step 2. Updated lock phase time formula to (512 × T
OSCIN
)............................. 528
• Section 14.5.2.2: Added formula to last sentence of second paragraph: T
Enable
= 150 × T
OSCIN
.............................. 529
• Section 14.5.2.2: Deleted table....................................................................................................... 529
• Section 14.5.2.3: Added formula to last sentence of paragraph: T
ODPLL
= 3 × T
OSCIN
........................................... 529
• Section 14.5.2.3: Deleted table....................................................................................................... 529
• Table 14-3: Changed table title. Changed table format ........................................................................... 530
• Table 14-3: Updated lock phase time formula to (512 × T
OSCIN
).................................................................. 530
• Section 14.5.4: Added last sentence to step 3 in both paragraphs.............................................................. 532
• Figure 14-11: Corrected symbols in figure.......................................................................................... 539
• Figure 14-11: Changed PF block to CP............................................................................................. 539
• Section 14.8: Changed step 3, second sentence .................................................................................. 540
• Chapter 15: Dual-Clock Comparator (DCC) Module ........................................................................... 542
• Figure 15-12: Updated Read/Write value of DONE and ERR bits to R/W1CP-0.............................................. 553
• Figure 15-12: Updated LEGEND to include W1CP................................................................................ 553
• Table 15-8: Corrected table title...................................................................................................... 554
• Table 15-11: Corrected table title .................................................................................................... 556
• Table 15-11: Changed Description of KEY bit for Value = Any other value.................................................... 556
• Chapter 16: Error Signaling Module (ESM)...................................................................................... 558
• Section 16.1.2: Changed first paragraph............................................................................................ 559
• Figure 16-17: Updated Read/Write value of bits to R/W1CP-X/0................................................................ 569
• Figure 16-18: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 569
• Figure 16-19: Updated Read/Write value of bits to R/W1CP-X/0................................................................ 570
• Figure 16-26: Updated Read/Write value of bits to R/W1CP-X/0................................................................ 574
• Figure 16-33: Updated Read/Write value of bits to R/W1CP-X/0................................................................ 578
• Figure 16-40: Updated Read/Write value of bits to R/W1CP-X/0................................................................ 582
• Chapter 17: Real-Time Interrupt (RTI) Module .................................................................................. 583
• Equation 24: Corrected first eqution (if RTICPUCy ≠ 0) .......................................................................... 587
• Section 17.2.5.1: Changed first paragraph ......................................................................................... 592
• Figure 17-18: Updated Read/Write value of bits to R/WP-0...................................................................... 601
• Figure 17-18: Updated LEGEND to include WP ................................................................................... 601
• Figure 17-38: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 615
• Figure 17-41: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 618
• Chapter 18: Cyclic Redundancy Check (CRC) Controller Module.......................................................... 625
• Figure 18-3: Changed MCRC Controller to CRC Controller...................................................................... 632
• Figure 18-4: Changed MCRC Controller to CRC Controller...................................................................... 632
• Chapter 19: Vectored Interrupt Manager (VIM) Module ....................................................................... 662
• Section 19.5: Added NOTE ........................................................................................................... 672
To Next Page
Loading...
