Revision History
www.ti.com
2200
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Revision History
• Figure 19-14: Corrected reset value of Interrupt Vector Table offset bits 15-9 ................................................ 683
• Table 19-8: Corrected Description of Interrupt Vector Table offset bits. Reads are always FFF8 2xxxh .................. 683
• Section 19.9.11: Updated LEGEND to include WP................................................................................ 688
• Figure 19-31: Updated LEGEND to include WP ................................................................................... 689
• Table 19-17: Corrected table title .................................................................................................... 689
• Chapter 20: Direct Memory Access Controller (DMA) Module .............................................................. 696
• Chapter 20: Global: Changed index pointer to offset value ...................................................................... 696
• Section 20.1.1: Updated eighth bullet ............................................................................................... 697
• Section 20.2.2: Changed second bullet ............................................................................................. 700
• Section 20.2.3: Deleted last sentence in second paragraph ..................................................................... 701
• Figure 20-5: Updated figure (changed Index Pointer to Offset Value) .......................................................... 702
• Section 20.2.7: Corrected second bullet. in first paragraph. The DMA controller can handle up to 48 DMA Request
lines ...................................................................................................................................... 710
• Section 20.2.7: Added last two paragraphs......................................................................................... 710
• Table 20-3: Added table. Subsequent tables renumbered ....................................................................... 710
• Section 20.2.9: Deleted fifth bullet (Bus error (BER) interrupt)................................................................... 712
• Section 20.2.9: Added fifth bullet (External imprecise error on read) ........................................................... 712
• Section 20.2.9: Added sixth bullet (External imprecise error on write).......................................................... 712
• Section 20.2.9: Changed NOTE. Deleted BER references....................................................................... 712
• Figure 20-14: Deleted BERA error signal. Added SCR block .................................................................... 713
• Figure 20-15: Changed output of OR gate to FTCA............................................................................... 713
• Figure 20-15: Changed footnote. Deleted BER reference........................................................................ 713
• Section 20.2.12Changed fifth paragraph............................................................................................ 715
• Section 20.2.18: Changed second paragraph...................................................................................... 719
• Table 20-7: Deleted BER Interrupt Mapping Register (BERMAP), BERA Interrupt Channel Offset Register
(BERAOFFSET), and BERB Interrupt Channel Offset Register (BERBOFFSET). Subsequent subsections, figures, and
tables renumbered ..................................................................................................................... 721
• Table 20-9: Updated Description of DMA_RES bit. (Writing a zero to this bit has no effect.) ............................... 724
• Figure 20-23: Updated Read/Write value of HWCHENA bit to R/WP-0 ........................................................ 727
• Figure 20-24: Updated Read/Write value of HWCHDIS bit to R/WP-0 ......................................................... 727
• Figure 20-25: Updated Read/Write value of SWCHENA bit to R/WP-0 ........................................................ 728
• Figure 20-26: Updated Read/Write value of SWCHDIS bit to R/WP-0.......................................................... 728
• Figure 20-27: Updated Read/Write value of CPS bit to R/WP-0................................................................. 729
• Figure 20-28: Updated Read/Write value of CPR bit to R/WP-0................................................................. 729
• Figure 20-29: Updated Read/Write value of GCHIE bit to R/WP-0.............................................................. 730
• Figure 20-30: Updated Read/Write value of GCHID bit to R/WP-0.............................................................. 730
• Table 20-21: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 731
• Table 20-21: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 731
• Table 20-22: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 732
• Table 20-22: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 732
• Table 20-23: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 733
• Table 20-23: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 733
• Table 20-24: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 734
• Table 20-24: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 734
• Table 20-25: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 735
• Table 20-25: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 735
• Table 20-26: Changed Description of all bits. Corrected channel number ..................................................... 736
• Table 20-26: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 736
• Table 20-26: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 736
• Table 20-27: Changed Description of all bits. Corrected channel number ..................................................... 737
• Table 20-27: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 737
• Table 20-27: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 737
• Table 20-28: Changed Description of all bits for Value = 2Fh. DMA request line 47 triggers channel ..................... 738
• Table 20-28: Updated Value column for all bits. Added 30h-3Fh = Reserved................................................. 738
To Next Page
Loading...
