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53
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Figures
23-187. WCAP Control Field (C31:C0) ....................................................................................... 1127
23-188. WCAP Data Field (D31:D0) .......................................................................................... 1127
23-189. WCAPE Program Field (P31:P0) .................................................................................... 1129
23-190. WCAPE Control Field (C31:C0)...................................................................................... 1129
23-191. WCAPE Data Field (D31:D0)......................................................................................... 1129
24-1. System Block Diagram ................................................................................................. 1133
24-2. HTU Block Diagram..................................................................................................... 1134
24-3. Example of a HTU Transfer............................................................................................ 1134
24-4. Single Buffer Timing and Memory Representation ................................................................. 1136
24-5. Timing Example for Circular Buffer Mode............................................................................ 1136
24-6. Dual Buffer Timing ...................................................................................................... 1137
24-7. Timing Example for Auto Switch Buffer Mode....................................................................... 1138
24-8. Timing for Disabling Control Packets................................................................................. 1139
24-9. Timing Example Including Lost Requests............................................................................ 1140
24-10. Timing that Generates No Request Lost Error ...................................................................... 1141
24-11. Timing that Generates a Request Lost Error ........................................................................ 1141
24-12. Timing Example for Two WCAP Instructions ........................................................................ 1142
24-13. Timing of the WCAP, ECNT, PCNT Example ....................................................................... 1145
24-14. Global Control Register (HTU GC) [offset = 00]..................................................................... 1149
24-15. Control Packet Enable Register (HTU CPENA) [offset = 04h] .................................................... 1150
24-16. Control Packet (CP) Busy Register 0 (HTU BUSY0) [offset = 08h] .............................................. 1151
24-17. Control Packet (CP) Busy Register 1 (HTU BUSY1) [offset = 0Ch].............................................. 1152
24-18. Control Packet (CP) Busy Register 2 (HTU BUSY2) [offset = 10h] .............................................. 1152
24-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h] .............................................. 1153
24-20. Active Control Packet and Error Register (HTU ACPE) [offset = 18h] ........................................... 1153
24-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h] ............................... 1155
24-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h] ......................................... 1156
24-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h] ....................................... 1156
24-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch]......................................................... 1157
24-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h]......................................................... 1158
24-26. Interrupt Offset Register 1 (HTU INTOFF1) [offset = 38h]......................................................... 1159
24-27. Buffer Initialization Mode Register (HTU BIM) [offset = 3Ch] ..................................................... 1160
24-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h] ...................................................... 1162
24-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) [offset = 44h] ................................................ 1162
24-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h]..................................................... 1163
24-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch] ...................................... 1164
24-32. Memory Protection 1 End Address Register (HTU MP1E) [offset = 50h]........................................ 1164
24-33. Debug Control Register (HTU DCTRL) [offset = 54h].............................................................. 1165
24-34. Watch Point Register (HTU WPR) [offset = 58h] ................................................................... 1166
24-35. Watch Mask Register (HTU WMR) [offset = 5Ch] .................................................................. 1166
24-36. Module Identification Register (HTU ID) [offset = 60h]............................................................. 1167
24-37. Parity Control Register (HTU PCR) [offset = 64h] .................................................................. 1168
24-38. Parity Address Register (HTU PAR) [offset = 68h] ................................................................. 1169
24-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]................................... 1170
24-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h]....................................... 1173
24-41. Memory Protection End Address Register (HTU MP0E) [offset = 78h] .......................................... 1173
24-42. Initial Full Address A Register (HTU IFADDRA) .................................................................... 1175
24-43. Initial Full Address B Register (HTU IFADDRB) .................................................................... 1175
24-44. Initial N2HET Address and Control Register (HTU IHADDRCT).................................................. 1176
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