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54
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Figures
24-45. Initial Transfer Count Register (HTU ITCOUNT).................................................................... 1177
24-46. Current Full Address A Register (HTU CFADDRA) ................................................................ 1178
24-47. Current Full Address B Register (HTU CFADDRB) ................................................................ 1179
24-48. Current Frame Count Register (HTU CFCOUNT) .................................................................. 1180
25-1. I/O Function Quick Start Flow Chart.................................................................................. 1185
25-2. Interrupt Generation Function Quick Start Flow Chart ............................................................. 1186
25-3. GIO Module Diagram ................................................................................................... 1187
25-4. GIO Block Diagram ..................................................................................................... 1189
25-5. GIO Global Control Register (GIOGCR0) [offset = 00h] ........................................................... 1192
25-6. GIO Interrupt Detect Register (GIOINTDET) [offset = 08h]........................................................ 1193
25-7. GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch] .......................................................... 1194
25-8. GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h] ................................................. 1195
25-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]............................................... 1196
25-10. GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h]....................................................... 1197
25-11. GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch] ...................................................... 1199
25-12. GIO Interrupt Flag Register (GIOFLG) [offset = 20h]............................................................... 1200
25-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h].................................................................... 1201
25-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h].................................................................... 1202
25-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch].............................................................. 1203
25-16. GIO Emulation 2 Register (GIOEMU2) [offset = 30h] .............................................................. 1204
25-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h]................................................. 1205
25-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h] ..................................................... 1205
25-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch] ............................................... 1206
25-20. GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h]..................................................... 1206
25-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h] .................................................. 1207
25-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h] ................................................... 1207
25-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch].............................................. 1208
25-24. GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h]..................................................... 1208
26-1. FlexRay Module Block Diagram....................................................................................... 1212
26-2. FlexRay Module Blocks ................................................................................................ 1214
26-3. Transfer Unit ............................................................................................................. 1216
26-4. FlexRay Transfer Unit Operation Principle........................................................................... 1217
26-5. FlexRay Transfer Unit Operation Principle for Transfer FSM (simplified) ....................................... 1218
26-6. FlexRay Transfer Unit Operation Principle for Event FSM (simplified)........................................... 1219
26-7. Example: FTU Read Transfer of 6 Words ........................................................................... 1221
26-8. Example: FTU Write Transfer of 6 Words............................................................................ 1221
26-9. Transfer Start Address to Message Buffer Number Assignment ................................................. 1223
26-10. Structure of Communication Cycle.................................................................................... 1226
26-11. Configuration of NIT Start and Offset Correction Start ............................................................. 1227
26-12. Overall State Diagram of Communication Controller ............................................................... 1231
26-13. Structure of POC State WAKEUP .................................................................................... 1235
26-14. Timing of Wake Up Pattern ............................................................................................ 1237
26-15. State Diagram Time-Triggered Startup............................................................................... 1239
26-16. FIFO Status: Empty, Not Empty, and Overrun ...................................................................... 1250
26-17. Host Access to Message RAM ........................................................................................ 1252
26-18. Double Buffer Structure Input Buffer.................................................................................. 1253
26-19. Swapping of IBCM and IBCR Bits .................................................................................... 1253
26-20. Double Buffer Structure Output Buffer................................................................................ 1255
26-21. Swapping of OBCM and OBCR Bits.................................................................................. 1255
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