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55
SPNU563A–March 2018
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List of Figures
26-22. Access to Transient Buffer RAMs..................................................................................... 1258
26-23. Configuration Example of Message Buffers in the Message RAM ............................................... 1259
26-24. Header Section of Message Buffer in Message RAM.............................................................. 1260
26-25. Example Structure of Data Partition in Message RAM............................................................. 1262
26-26. Parity/ECC Structure.................................................................................................... 1263
26-27. ECC Generation and Check ........................................................................................... 1264
26-28. ECC Syndrome Table .................................................................................................. 1265
26-29. ECC Syndrome Table (TCR) .......................................................................................... 1265
26-30. Transfer Unit (TU) Interrupt Structure ................................................................................ 1270
26-31. Communication Controller (CC) Interrupt Structure ................................................................ 1272
26-32. Global Static Number 0 (GSN0) [offset_TU = 00h] ................................................................. 1279
26-33. Global Static Number 1 (GSN1) [offset_TU = 04h] ................................................................. 1279
26-34. Global Control Set (GCS) [offset_TU = 10h] ........................................................................ 1280
26-35. Global Control Reset (GCR) [offset_TU = 14h] ..................................................................... 1280
26-36. Transfer Status Current Buffer (TSCB) [offset_TU = 18h] ......................................................... 1283
26-37. Last Transferred Buffer to Communication Controller (LTBCC) [offset_TU = 1Ch] ............................ 1284
26-38. Last Transferred Buffer to System Memory (LTBSM) [offset_TU = 20h] ........................................ 1284
26-39. Transfer Base Address (TBA) [offset_TU = 24h].................................................................... 1285
26-40. Next Transfer Base Address (NTBA) [offset_TU = 28h] ........................................................... 1285
26-41. Base Address of Mirrored Status (BAMS) [offset_TU = 2Ch] ..................................................... 1286
26-42. Start Address of Memory Protection (SAMP) [offset_TU = 30h].................................................. 1287
26-43. End Address of Memory Protection (EAMP) [offset_TU = 34h]................................................... 1287
26-44. Transfer to System Memory Occurred 1 (TSMO1) [offset_TU = 40h] ........................................... 1288
26-45. Transfer to System Memory Occurred 2 (TSMO2) [offset_TU = 44h] ........................................... 1288
26-46. Transfer to System Memory Occurred 3 (TSMO3) [offset_TU = 48h] ........................................... 1288
26-47. Transfer to System Memory Occurred 4 (TSMO4) [offset_TU = 4Ch] ........................................... 1288
26-48. Transfer to Communication Controller Occurred 1 (TCCO1) [offset_TU = 50h] ................................ 1290
26-49. Transfer to Communication Controller Occurred 2 (TCCO2) [offset_TU = 54h] ................................ 1290
26-50. Transfer to Communication Controller Occurred 3 (TCCO3) [offset_TU = 58h] ................................ 1290
26-51. Transfer to Communication Controller Occurred 4 (TCCO4) [offset_TU = 5Ch]................................ 1290
26-52. Transfer Occurred Offset (TOOFF) [offset_TU = 60h] ............................................................. 1292
26-53. TCR Single-Bit Error Status (TSBESTAT) [offset_TU = 6Ch]..................................................... 1293
26-54. ECC Error Address (PEADR) [offset_TU = 70h] .................................................................... 1294
26-55. Transfer Error Interrupt Flag (TEIF) [offset_TU = 74h]............................................................. 1295
26-56. Transfer Error Interrupt Enable Set (TEIRES) [offset_TU = 78h] ................................................. 1297
26-57. Transfer Error Interrupt Enable Reset (TEIRER) [offset_TU = 7Ch] ............................................. 1298
26-58. Trigger Transfer to System Memory Set 1 (TTSMS1) [offset_TU = 80h]........................................ 1299
26-59. Trigger Transfer to System Memory Reset 1 (TTSMR1) [offset_TU = 84h]..................................... 1299
26-60. Trigger Transfer to System Memory Set 2 (TTSMS2) [offset_TU = 88h]........................................ 1300
26-61. Trigger Transfer to System Memory Reset 2 (TTSMR2) [offset_TU = 8Ch] .................................... 1300
26-62. Trigger Transfer to System Memory Set 3 (TTSMS3) [offset_TU = 90h]........................................ 1301
26-63. Trigger Transfer to System Memory Reset 3 (TTSMR3) [offset_TU = 94h]..................................... 1301
26-64. Trigger Transfer to System Memory Set 4 (TTSMS4) [offset_TU = 98h]........................................ 1302
26-65. Trigger Transfer to System Memory Reset 4 (TTSMR4) [offset_TU = 9Ch] .................................... 1302
26-66. Trigger Transfer to Communication Controller Set 1 (TTCCS1) [offset_TU = A0h] ............................ 1303
26-67. Trigger Transfer to Communication Controller Reset 1 (TTCCR1) [offset_TU = A4h]......................... 1303
26-68. Trigger Transfer to Communication Controller Set 2 (TTCCS2) [offset_TU = A8h] ............................ 1304
26-69. Trigger Transfer to Communication Controller Reset 2 (TTCCR2) [offset_TU = ACh] ........................ 1304
26-70. Trigger Transfer to Communication Controller Set 3 (TTCCS3) [offset_TU = B0h] ............................ 1305
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