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56
SPNU563A–March 2018
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List of Figures
26-71. Trigger Transfer to Communication Controller Reset 3 (TTCCR3) [offset_TU = B4h]......................... 1305
26-72. Trigger Transfer to Communication Controller Set 4 (TTCCS4) [offset_TU = B8h] ............................ 1306
26-73. Trigger Transfer to Communication Controller Reset 4 (TTCCR4) [offset_TU = BCh] ........................ 1306
26-74. Enable Transfer on Event to System Memory Set 1 (ETESMS1) [offset_TU = C0h] .......................... 1307
26-75. Enable Transfer on Event to System Memory Reset 1 (ETESMR1) [offset_TU = C4h] ....................... 1307
26-76. Enable Transfer on Event to System Memory Set 2 (ETESMS2) [offset_TU = C8h] .......................... 1308
26-77. Enable Transfer on Event to System Memory Reset 2 (ETESMR2) [offset_TU = CCh] ...................... 1308
26-78. Enable Transfer on Event to System Memory Set 3 (ETESMS3) [offset_TU = D0h] .......................... 1309
26-79. Enable Transfer on Event to System Memory Reset 3 (ETESMR3) [offset_TU = D4h] ....................... 1309
26-80. Enable Transfer on Event to System Memory Set 4 (ETESMS4) [offset_TU = D8h] .......................... 1310
26-81. Enable Transfer on Event to System Memory Reset 4 (ETESMR4) [offset_TU = DCh] ...................... 1310
26-82. Clear on Event to System Memory Set 1 (CESMS1) [offset_TU = E0h]......................................... 1311
26-83. Clear on Event to System Memory Reset 1 (CESMR1) [offset_TU = E4h] ..................................... 1311
26-84. Clear on Event to System Memory Set 2 (CESMS2) [offset_TU = E8h]......................................... 1312
26-85. Clear on Event to System Memory Reset 2 (CESMR2) [offset_TU = ECh] ..................................... 1312
26-86. Clear on Event to System Memory Set 3 (CESMS3) [offset_TU = F0h]......................................... 1313
26-87. Clear on Event to System Memory Reset 3 (CESMR3) [offset_TU = F4h]...................................... 1313
26-88. Clear on Event to System Memory Set 4 (CESMS4) [offset_TU = F8h]......................................... 1314
26-89. Clear on Event to System Memory Reset 4 (CESMR4) [offset_TU = FCh] ..................................... 1314
26-90. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) [offset_TU = 100h]........................... 1315
26-91. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) [offset_TU = 104h]........................ 1315
26-92. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) [offset_TU = 108h]........................... 1316
26-93. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) [offset_TU = 10Ch] ....................... 1316
26-94. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) [offset_TU = 110h]........................... 1317
26-95. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) [offset_TU = 114h]........................ 1317
26-96. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) [offset_TU = 118h]........................... 1318
26-97. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) [offset_TU = 11Ch] ....................... 1318
26-98. Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1) [offset_TU = 120h] ............... 1319
26-99. Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1) [offset_TU = 124h] ............ 1319
26-100. Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2) [offset_TU = 128h].............. 1320
26-101. Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2) [offset_TU = 12Ch] .......... 1320
26-102. Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3) [offset_TU = 130h].............. 1321
26-103. Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3) [offset_TU = 134h]........... 1321
26-104. Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4) [offset_TU = 138h].............. 1322
26-105. Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4) [offset_TU = 13Ch] .......... 1322
26-106. Transfer Configuration RAM (TCR) [offset_TU_RAM = 0000h - 01FFh] ....................................... 1323
26-107. ECC Information in TCR ECC Test Mode [offset_TU_RAM = 200h-3FCh].................................... 1324
26-108. Message Buffer Assignment.......................................................................................... 1325
26-109. ECC Control Register (ECC_CTRL) [offset_CC = 00h] .......................................................... 1328
26-110. ECC Diagnostic Status Register (ECCDSTAT) [offset_CC = 04h].............................................. 1329
26-111. ECC Test Register (ECCTEST) [offset_CC = 08h]................................................................ 1331
26-112. Single-Bit Error Status Register (SBESTAT) [offset_CC = 0Ch] ................................................ 1332
26-113. Test Register 1 (TEST1) [offset_CC = 10h] ........................................................................ 1334
26-114. Test Register 2 (TEST2) [offset_CC = 14h] ........................................................................ 1338
26-115. Test Mode Access to Communication Controller RAM Blocks .................................................. 1339
26-116. Lock Register (LCK) [offset_CC = 1Ch]............................................................................. 1340
26-117. Error Interrupt Register (EIR) [offset_CC = 20h]................................................................... 1341
26-118. Status Interrupt Register (SIR) [offset_CC = 24h]................................................................. 1343
26-119. Error Interrupt Line Select Register (EILS) [offset_CC = 28h] ................................................... 1346
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