Texas Instruments TMS570LC4357 - Page 57

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57
SPNU563A–March 2018
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List of Figures
26-120. Status Interrupt Line Select Register (SILS) [offset_CC = 2Ch]................................................. 1348
26-121. Error Interrupt Enable Set/Reset Register (EIES/EIER) [offset_CC = 30h/34h]............................... 1350
26-122. Status Interrupt Enable Set/Reset Register (SIES/SIER) [offset_CC = 38h/3Ch]............................. 1352
26-123. Interrupt Line Enable Register (ILE) [offset_CC = 40h]........................................................... 1354
26-124. Timer 0 Configuration Register (T0C) [offset_CC = 44h]......................................................... 1355
26-125. Timer 1 Configuration Register (T1C) [offset_CC = 48h]......................................................... 1356
26-126. Stop Watch Register 1 (STPW1) [offset_CC = 4Ch].............................................................. 1357
26-127. Stop Watch Register 2 (STPW2) [offset_CC = 50h] .............................................................. 1358
26-128. SUC Configuration Register 1 (SUCC1) [offset_CC = 80h]...................................................... 1359
26-129. SUC Configuration Register 2 (SUCC2) [offset_CC = 84h]...................................................... 1363
26-130. SUC Configuration Register 3 (SUCC3) [offset_CC = 88h]...................................................... 1364
26-131. NEM Configuration Register (NEMC) [offset_CC = 8Ch]......................................................... 1364
26-132. PRT Configuration Register 1 (PRTC1) [offset_CC = 90h]....................................................... 1365
26-133. PRT Configuration Register 2 (PRTC2) [offset_CC = 94h]....................................................... 1366
26-134. MHD Configuration Register (MHDC) [offset_CC = 98h]......................................................... 1367
26-135. GTU Configuration Register 1 (GTUC1) [offset_CC = A0h]...................................................... 1368
26-136. GTU Configuration Register 2 (GTUC2) [offset_CC = A4h]...................................................... 1368
26-137. GTU Configuration Register 3 (GTUC3) [offset_CC = A8h]...................................................... 1369
26-138. GTU Configuration Register 4 (GTUC4) [offset_CC = ACh] ..................................................... 1370
26-139. GTU Configuration Register 5 (GTUC5) [offset_CC = B0h]...................................................... 1370
26-140. GTU Configuration Register 6 (GTUC6) [offset_CC = B4h]...................................................... 1371
26-141. GTU Configuration Register 7 (GTUC7) [offset_CC = B8h]...................................................... 1371
26-142. GTU Configuration Register 8 (GTUC8) [offset_CC = BCh] ..................................................... 1372
26-143. GTU Configuration Register 9 (GTUC9) [offset_CC = C0h] ..................................................... 1372
26-144. GTU Configuration Register 10 (GTUC10) [offset_CC = C4h] .................................................. 1373
26-145. GTU Configuration Register 11 (GTUC11) [offset_CC = C8h] .................................................. 1374
26-146. Communication Controller Status Vector Register (CCSV) [offset_CC = 100h]............................... 1375
26-147. Communication Controller Error Vector Register (CCEV) [offset_CC = 104h] ................................ 1377
26-148. Slot Counter Vector Register (SCV) [offset_CC = 110h] ......................................................... 1378
26-149. Macrotick and Cycle Counter Register (MTCCV) [offset_CC = 114h] .......................................... 1378
26-150. Rate Correction Value Register (RCV) [offset_CC = 118h] ...................................................... 1379
26-151. Offset Correction Value Register (OCV) [offset_CC = 11Ch] .................................................... 1379
26-152. Sync Frame Status Register (SFS) [offset_CC = 120h] .......................................................... 1380
26-153. Symbol Window and NIT Status Register (SWNIT) [offset_CC = 124h] ....................................... 1381
26-154. Aggregated Channel Status Register (ACS) [offset_CC = 128h]................................................ 1382
26-155. Even Sync ID Registers (ESIDn) [offset_CC = 130h-168h]...................................................... 1384
26-156. Odd Sync ID Registers (OSIDn) [offset_CC = 170h-1A8h] ...................................................... 1385
26-157. Network Management Vector Registers (NMVn) [offset_CC = 1B0h-1B8h] ................................... 1386
26-158. Message RAM Configuration Register (MRC) [offset_CC = 300h].............................................. 1387
26-159. FIFO Rejection Filter Register (FRF) [offset_CC = 304h] ........................................................ 1389
26-160. FIFO Rejection Filter Mask Register (FRFM) [offset_CC = 308h]............................................... 1390
26-161. FIFO Critical Level Register (FCL) [offset_CC = 30Ch] .......................................................... 1390
26-162. Message Handler Status (MHDS) [offset_CC = 310h]............................................................ 1391
26-163. Last Dynamic Transmit Slot (LDTS) [offset_CC = 314h] ......................................................... 1392
26-164. FIFO Status Register (FSR) [offset_CC = 318h] .................................................................. 1393
26-165. Message Handler Constraints Flags (MHDF) [offset_CC = 31Ch] .............................................. 1394
26-166. Transmission Request Register 4 (TXRQ4) [offset_CC = 32Ch]................................................ 1396
26-167. Transmission Request Register 3 (TXRQ3) [offset_CC = 328h] ................................................ 1396
26-168. Transmission Request Register 2 (TXRQ2) [offset_CC = 324h] ................................................ 1396