Texas Instruments TMS570LC4357 - Page 58

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58
SPNU563A–March 2018
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List of Figures
26-169. Transmission Request Register 1 (TXRQ1) [offset_CC = 320h] ................................................ 1396
26-170. New Data Register 4 (NDAT4) [offset_CC = 33Ch]............................................................... 1397
26-171. New Data Register 3 (NDAT3) [offset_CC = 338h] ............................................................... 1397
26-172. New Data Register 2 (NDAT2) [offset_CC = 334h] ............................................................... 1397
26-173. New Data Register 1 (NDAT1) [offset_CC = 330h] ............................................................... 1397
26-174. Message Buffer Status Changed Register 4 (MBSC4) [offset_CC = 34Ch] ................................... 1399
26-175. Message Buffer Status Changed Register 3 (MBSC3) [offset_CC = 348h].................................... 1399
26-176. Message Buffer Status Changed Register 2 (MBSC2) [offset_CC = 344h].................................... 1399
26-177. Message Buffer Status Changed Register 1 (MBSC1) [offset_CC = 340h].................................... 1399
26-178. Core Release Register (CREL) [offset_CC = 3F0h]............................................................... 1400
26-179. Endian Register (ENDN) [offset_CC = 3F4h] ...................................................................... 1400
26-180. Write Data Section Registers (WRDSn) [offset_CC = 400h-4FCh] ............................................. 1401
26-181. Write Header Section Register 1 (WRHS1) [offset_CC = 500h]................................................. 1402
26-182. Write Header Section Register 2 (WRHS2) [offset_CC = 504h]................................................. 1403
26-183. Write Header Section Register 3 (WRHS3) [offset_CC = 508h]................................................. 1404
26-184. Input Buffer Command Mask Register (IBCM) [offset_CC = 510h] ............................................. 1405
26-185. Input Buffer Command Request Register (IBCR) [offset_CC = 514h].......................................... 1406
26-186. Read Data Section Registers (RDDSn) [offset_CC = 600h-6FCh].............................................. 1407
26-187. Read Header Section Register 1 (RDHS1) [offset_CC = 700h] ................................................. 1408
26-188. Read Header Section Register 2 (RDHS2) [offset_CC = 704h] ................................................. 1409
26-189. Read Header Section Register 3 (RDHS3) [offset_CC = 708h] ................................................. 1410
26-190. Message Buffer Status Register (MBS) [offset_CC = 70Ch]..................................................... 1411
26-191. Output Buffer Command Mask Register (OBCM) [offset_CC = 700h].......................................... 1414
26-192. Output Buffer Command Mask Register (OBCR) [offset_CC = 714h] .......................................... 1415
27-1. DCAN Block Diagram................................................................................................... 1419
27-2. Bit Timing................................................................................................................. 1421
27-3. CAN Bit-timing Configuration .......................................................................................... 1426
27-4. Structure of a Message Object ........................................................................................ 1428
27-5. Message RAM Representation in Debug/Suspend Mode ......................................................... 1431
27-6. Message RAM Representation in RAM Direct Access Mode ..................................................... 1431
27-7. ECC RAM Representation ............................................................................................. 1432
27-8. Data Transfer Between IF1 / IF2 Registers and Message RAM.................................................. 1434
27-9. Initialization of a Transmit Object ..................................................................................... 1436
27-10. Initialization of a Single Receive Object for Data Frames ......................................................... 1436
27-11. Initialization of a Single Receive Object for Remote Frames...................................................... 1437
27-12. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 1442
27-13. CAN Interrupt Topology 1 .............................................................................................. 1445
27-14. CAN Interrupt Topology 2 .............................................................................................. 1446
27-15. Local Power Down Mode Flow Diagram ............................................................................. 1448
27-16. CAN Core in Silent Mode .............................................................................................. 1449
27-17. CAN Core in Loop Back Mode ........................................................................................ 1450
27-18. CAN Core in External Loop Back Mode.............................................................................. 1451
27-19. CAN Core in Loop Back Combined with Silent Mode .............................................................. 1452
27-20. CAN Control Register (DCAN CTL) [offset = 00h] .................................................................. 1456
27-21. Error and Status Register (DCAN ES) [offset = 04h]............................................................... 1459
27-22. Error Counter Register (DCAN ERRC) [offset = 08h] .............................................................. 1461
27-23. Bit Timing Register (DCAN BTR) [offset = 0Ch] .................................................................... 1462
27-24. Interrupt Register (DCAN INT) [offset = 10h]........................................................................ 1463
27-25. Test Register (DCAN TEST) [offset = 14h] .......................................................................... 1464