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50
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Figures
23-40. SCNT Stepping Compensation ......................................................................................... 999
23-41. ACNT During Acceleration and Deceleration........................................................................ 1000
23-42. Singularity Check, ACNT Reset and Timing Associated........................................................... 1001
23-43. Example of HWAG Start Sequence................................................................................... 1002
23-44. Code ...................................................................................................................... 1003
23-45. Gap Verification Criteria For a 60-2 Toothed Wheel ............................................................... 1004
23-46. Using the ARST Bit in a Toothed Wheel Without Singularity...................................................... 1005
23-47. Windowing Filter for Toothed Wheel Input on Falling Active Edge ............................................... 1006
23-48. Filtering During Singularity Tooth .................................................................................... 1007
23-49. HWAG Interrupt Block Diagram ....................................................................................... 1008
23-50. Hardware Angle Generator/High End Timer Interface ............................................................. 1010
23-51. Angle Count Within the HWAG at Resolution Clock................................................................ 1010
23-52. Angle Count Within the NHET With Increments .................................................................... 1011
23-53. Compare Without ACMP Instruction.................................................................................. 1011
23-54. Example of ACMP Compare Within the NHET...................................................................... 1012
23-55. NHET Interface Block Diagram........................................................................................ 1013
23-56. Global Configuration Register (HETGCR) [offset = 00h]........................................................... 1018
23-57. Prescale Factor Register (HETPFR).................................................................................. 1020
23-58. N2HET Current Address (HETADDR)................................................................................ 1021
23-59. Offset Index Priority Level 1 Register (HETOFF1).................................................................. 1021
23-60. Offset Index Priority Level 2 Register (HETOFF2).................................................................. 1022
23-61. Interrupt Enable Set Register (HETINTENAS) ..................................................................... 1023
23-62. Interrupt Enable Clear (HETINTENAC) .............................................................................. 1023
23-63. Exception Control Register (HETEXC1).............................................................................. 1024
23-64. Exception Control Register 2 (HETEXC2) ........................................................................... 1025
23-65. Interrupt Priority Register (HETPRY) ................................................................................ 1026
23-66. Interrupt Flag Register (HETFLG)..................................................................................... 1026
23-67. AND Share Control Register (HETAND) ............................................................................ 1027
23-68. HR Share Control Register (HETHRSH) ............................................................................ 1028
23-69. XOR Share Control Register (HETXOR)............................................................................. 1029
23-70. Request Enable Set Register (HETREQENS) ...................................................................... 1030
23-71. Request Enable Clear Register (HETREQENC) ................................................................... 1030
23-72. Request Destination Select Register (HETREQDS) [offset = FFF7 B844h]..................................... 1031
23-73. N2HET Direction Register (HETDIR) ................................................................................. 1032
23-74. N2HET Data Input Register (HETDIN) ............................................................................... 1033
23-75. N2HET Data Output Register (HETDOUT) .......................................................................... 1033
23-76. N2HET Data Set Register (HETDSET)............................................................................... 1034
23-77. N2HET Data Clear Register (HETDCLR) ............................................................................ 1034
23-78. N2HET Open Drain Register (HETPDR) ............................................................................ 1035
23-79. N2HET Pull Disable Register (HETPULDIS) ....................................................................... 1035
23-80. N2HET Pull Select Register (HETPSL) .............................................................................. 1036
23-81. Parity Control Register (HETPCR).................................................................................... 1037
23-82. Parity Address Register (HETPAR)................................................................................... 1038
23-83. Parity Pin Register (HETPPR)......................................................................................... 1039
23-84. Suppression Filter Preload Register (HETSFPRLD) ............................................................... 1040
23-85. Suppression Filter Enable Register (HETSFENA).................................................................. 1040
23-86. Loop Back Pair Select Register (HETLBPSEL) ..................................................................... 1041
23-87. Loop Back Pair Direction Register (HETLBPDIR) .................................................................. 1042
23-88. N2HET Pin Disable Register (HETPINDIS).......................................................................... 1043
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