Texas Instruments TMS570LC4357 - Page 49

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SPNU563A–March 2018
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List of Figures
22-100. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) (offset =
190h) ....................................................................................................................... 948
22-101. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 194h) .... 948
22-102. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 198h) .... 949
22-103. ADC Event Group Current Count Register (ADEVCURRCOUNT) (offset = 19Ch) ............................ 950
22-104. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) (offset = 1A0h)............................ 950
22-105. ADC Group1 Current Count Register (ADG1CURRCOUNT) (offset = 1A4h)................................... 951
22-106. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) (offset = 1A8h).................................. 951
22-107. ADC Group2 Current Count Register (ADG2CURRCOUNT) (offset = 1ACh) .................................. 952
22-108. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) (offset = 1B0h).................................. 952
23-1. N2HET Block Diagram ................................................................................................... 955
23-2. Specialized Timer Micromachine ....................................................................................... 959
23-3. Program Flow Timings ................................................................................................... 960
23-4. Use of the Overflow Interrupt Flag (HETEXC2) ...................................................................... 961
23-5. Multi-Resolution Operation Flow Example ............................................................................ 962
23-6. Debug Control Configuration............................................................................................ 963
23-7. Prescaler Configuration .................................................................................................. 967
23-8. I/O Control ................................................................................................................. 970
23-9. N2HET Loop Resolution Structure for Each Bit ...................................................................... 971
23-10. Loop Resolution Instruction Execution Example ..................................................................... 972
23-11. HR I/O Architecture....................................................................................................... 973
23-12. Example of HR Structure Sharing for N2HET Pins 0/1.............................................................. 974
23-13. XOR-shared HR I/O ...................................................................................................... 975
23-14. Symmetrical PWM with XOR-sharing Output ......................................................................... 976
23-15. AND-shared HR I/O ...................................................................................................... 976
23-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0 ................................................................ 977
23-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1 .............................................................. 978
23-18. N2HET Input Edge Detection ........................................................................................... 979
23-19. ECMP Execution Timings................................................................................................ 980
23-20. High/Low Resolution Modes for ECMP and PWCNT ................................................................ 981
23-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow) ...................................... 982
23-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) .................................... 982
23-23. WCAP Instruction Timing ................................................................................................ 983
23-24. I/O Block Diagram Including Pull Control Logic....................................................................... 984
23-25. N2HET Pin Disable Feature Diagram.................................................................................. 985
23-26. Suppression Filter Counter Operation ................................................................................. 987
23-27. Interrupt Functionality on Instruction Level ............................................................................ 988
23-28. Interrupt Flag/Priority Level Architecture............................................................................... 989
23-29. Request Line Assignment Example .................................................................................... 990
23-30. Operation of N2HET Count Instructions ............................................................................... 991
23-31. SCNT Count Operation .................................................................................................. 991
23-32. ACNT Period Variation Compensations ............................................................................... 992
23-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) ............................................. 993
23-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration) ............................................. 994
23-35. Angle Generator Principle ............................................................................................... 995
23-36. Hardware Angle Generator Block Diagram............................................................................ 996
23-37. Angle Tick Generation Principle ........................................................................................ 997
23-38. New Angle Tick Generation Architecture .............................................................................. 998
23-39. Angle Generation Using Time Based Algorithm ...................................................................... 999