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SPNU563A–March 2018
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List of Tables
23-1. N2HET RAM Base Addresses .......................................................................................... 963
23-2. N2HET RAM Bank Structure............................................................................................ 964
23-3. Pin Safe State Upon Parity Error Detection........................................................................... 965
23-4. N2HET Parity Bit Mapping............................................................................................... 966
23-5. Prescale Factor Register Encoding .................................................................................... 967
23-6. Interpretation of the 7-Bit HR Data Field............................................................................... 968
23-7. Edge Detection Input Timing for Loop Resolution Instructions ..................................................... 979
23-8. Edge Detection Input Timing for High Resolution Instructions...................................................... 979
23-9. Input Buffer, Output Buffer, and Pull Control Behavior .............................................................. 985
23-10. N2HET Pin Disable Feature............................................................................................. 986
23-11. Pulse Length Examples for Suppression Filter ....................................................................... 987
23-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx..................................... 987
23-13. HWAG Interrupt Sources and Offset Values ........................................................................ 1008
23-14. HWAG Interrupt Descriptions.......................................................................................... 1009
23-15. N2HET Registers........................................................................................................ 1017
23-16. Global Configuration Register (HETGCR) Field Descriptions ..................................................... 1018
23-17. Prescale Factor Register (HETPFR) Field Descriptions ........................................................... 1020
23-18. N2HET Current Address (HETADDR) Field Descriptions ......................................................... 1021
23-19. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions ........................................... 1021
23-20. Interrupt Offset Encoding Format ..................................................................................... 1022
23-21. Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions ........................................... 1022
23-22. Interrupt Enable Set Register (HETINTENAS) Field Descriptions................................................ 1023
23-23. NHET Interrupt Enable Clear (HETINTENAC) Field Descriptions ................................................ 1023
23-24. Exception Control Register 1 (HETEXC1) Field Descriptions..................................................... 1024
23-25. Exception Control Register 2 (HETEXC2) Field Descriptions..................................................... 1025
23-26. Interrupt Priority Register (HETPRY) Field Descriptions........................................................... 1026
23-27. Interrupt Flag Register (HETFLG) Field Descriptions .............................................................. 1026
23-28. AND Share Control Register (HETAND) Field Descriptions....................................................... 1027
23-29. HR Share Control Register (HETHRSH) Field Descriptions....................................................... 1028
23-30. XOR Share Control Register (HETXOR) Field Descriptions ...................................................... 1029
23-31. Request Enable Set Register (HETREQENS) Field Descriptions ................................................ 1030
23-32. Request Enable Clear Register (HETREQENC) Field Descriptions.............................................. 1030
23-33. Request Destination Select Register (HETREQDS) Field Descriptions ......................................... 1031
23-34. N2HET Direction Register (HETDIR) Field Descriptions........................................................... 1032
23-35. N2HET Data Input Register (HETDIN) Field Descriptions......................................................... 1033
23-36. N2HET Data Output Register (HETDOUT) Field Descriptions.................................................... 1033
23-37. N2HET Data Set Register (HETDSET) Field Descriptions ........................................................ 1034
23-38. N2HET Data Clear Register (HETDCLR) Field Descriptions...................................................... 1034
23-39. N2HET Open Drain Register (HETPDR) Field Descriptions ...................................................... 1035
23-40. N2HET Pull Disable Register (HETPULDIS) Field Descriptions.................................................. 1035
23-41. N2HET Pull Select Register (HETPSL) Field Descriptions ........................................................ 1036
23-42. Parity Control Register (HETPCR) Field Descriptions.............................................................. 1037
23-43. Parity Address Register (HETPAR) Field Descriptions ............................................................ 1038
23-44. Parity Pin Register (HETPPR) Field Descriptions .................................................................. 1039
23-45. Known State on Parity Error ........................................................................................... 1039
23-46. Suppression Filter Preload Register (HETSFPRLD) Field Descriptions ......................................... 1040
23-47. Suppression Filter Enable Register (HETSFENA) Field Descriptions............................................ 1040
23-48. Loop Back Pair Select Register (HETLBPSEL) Field Descriptions............................................... 1041
23-49. Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions ............................................ 1042
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