hr = 2 HRP
hr
VCLK2
--------------------
2
32MHz
------------------= = =
lr =128
lr x HRP = 128 x 62.5ns = 8 sμ
ts = hr x lr = 2 x 128 = 256
hr = 2, lr = 128
HETPFR[31:0] = 0x00000701
62.5ns
N2HET Functional Description
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.2.3.1 Determining Loop Resolution
As an example, consider an application that requires high resolution of HRP = 62.5 ns, and loop resolution
of LRP = 8 μs, and needs at least 250 time slots for the N2HET application program.
Assuming VCLK2 = 32 MHz, the following shows which divide-by rates and which value in the Prescale
Factor Register (HETPFR) is required for the above requirements:
(29)
In the example above, if the loop resolution period needs to decrease from 8 μs to 4 μs, then only 128
time slots will be available for program execution. The program may need to be restructured as suggested
in Section 23.2.1.6.
23.2.3.2 The 7-Bit HR Data Field
The instruction execution examples of ECMP (Section 23.2.5.9), MCMP (Section 23.2.5.10), PCNT
(Section 23.2.5.12), PWCNT (Section 23.2.5.11), and WCAP (Section 23.2.5.13) show that the 7-bit HR
data field can generate or measure high resolution delays (HR delay) relative to the start of an LRP within
one N2HET loop LRP. The last section showed that:
LRP = lr × HRP
There are lr high resolution clock periods (HRP) within the N2HET loop resolution clock period (LRP). If lr
= 128 then the HR delay can range from 0 to127 HRP clocks within LRP and all 7 bits of the HR data field
are needed. Instead of being limited to measuring and triggering events based on the loop resolution clock
period (LRP) the HR extension allows measurements and events to be described in terms fractions of an
LRP (down to 1/128 of an LRP). The only limitation is that a maximum of one HR delay can be specified
per pin during each loop resolution period.
Table 23-6 shows which bits of the HR data field are not used by the high resolution IO structures if lr is
less than 128. In this case the non-relevant bits (LSBs) of the HR data fields will be one of the following:
• Written as 0 for HR capture (for PCNT, WCAP)
• Or interpreted as 0 for HR compare (for ECMP, MCMP. PWCNT)
(1)
X = Non-relevant bit (treated as '0')
Table 23-6. Interpretation of the 7-Bit HR Data Field
Loop Resolution
Prescale divide rate (lr)
Bits of the HR data field
(1)
HRP Cycles delay rangeD[6] D[5] D[4] D[3] D[2] D[1] D[0]
1 X X X X X X X 0
2 1/2 X X X X X X 0 to 1
4 1/2 1/4 X X X X X 0 to 3
8 1/2 1/4 1/8 X X X X 0 to 7
16 1/2 1/4 1/8 1/16 X X X 0 to 15
32 1/2 1/4 1/8 1/16 1/32 X X 0 to 31
64 1/2 1/4 1/8 1/16 1/32 1/64 X 0 to 63
128 1/2 1/4 1/8 1/16 1/32 1/64 1/128 0 to 127
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