User’s Manual L-14 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Power management 5-2 [1]
Idle mode 5-5 [1]
Mode definitions 5-2 [1]
Register PMG_CSR 5-3 [1]
Sleep mode 5-6 [1]
Summary 5-7 [1]
Processor subsystem
Core SFRs 2-10 [1]
Implementation-specific features
2-7 [1]
Interrupt system 2-8 [1]
Subsystem block diagram 2-1 [1]
R
Register overview and address map
18-1 [1]
Remote peripheral bus 6-19 [1]
Reset
Debug system reset 4-10 [1]
External hardware reset 4-7 [1]
Module behavior 4-10 [1]
Overview 4-1 [1]
Power-on reset 4-7 [1]
Registers
RST_REQ 4-5 [1]
RST_SR 4-3 [1]
Software reset 4-8 [1]
WDT reset 4-8 [1]
S
SCU
Miscellaneous registers
CHIPID 5-70 [1]
MANID 5-69 [1]
RTID 5-71 [1]
SCU_CON 5-64 [1]
SCU_STAT 5-67 [1]
Registers
Offset addresses 5-61 [1]
Overview 5-61 [1]
Sleep mode 5-6 [1]
Software configuration
in TC1796 devices 10-25 [1]
via SWOPT bits 10-24 [1]
SSC
Baud rate generation 20-18 [2],
20-48 [2]
Baud rate generation formulas
20-18 [2], 20-49 [2]
Block diagram 20-4 [2]
Chip select generation 20-21 [2]
DMA request outputs 20-60 [2]
Error detection 20-24 [2]
FIFO operation
Receive FIFO 20-14 [2]
Transmit FIFO 20-12 [2]
Transparent Mode 20-16 [2]
Full-duplex operation 20-6 [2]
Half-duplex operation 20-9 [2]
Interrupts 20-24 [2]
Module implementation 20-46 [2]–??
DMA request outputs 20-60 [2]
Interrupt registers 20-59 [2]
Module clock control 20-48 [2]
Port control 20-52 [2]
Registers 20-27 [2]–20-45 [2]
BR 20-39 [2]
CON 20-32 [2]
EFM 20-35 [2]
FSTAT 20-44 [2]
ID 20-29 [2]
Offset addresses 20-27 [2]
Overview 20-27 [2]
PISEL 20-30 [2]
RB 20-45 [2]
RXFCON 20-40 [2]
SSOC 20-37 [2]
SSOTC 20-38 [2]
STAT 20-34 [2]
TB 20-45 [2]
TXFCON 20-42 [2]
Slave select input operation 20-20 [2]
Slave select output operation 20-21 [2]
STM, see “System timer” 15-1 [1]
System clock output 3-41 [1]
System control unit, see “SCU”
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