User’s Manual L-15 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
System peripheral bus 6-19 [1]
System timer
Block diagram 15-3 [1]
Compare register operation 15-5 [1]
Interrupt control 15-6 [1]
Operation 15-1 [1]
Overview 15-1 [1]
Registers
Offset addresses 15-8 [1]
Overview 15-7 [1]
STM_CAP 15-14 [1]
STM_CLC 15-9 [1]
STM_CMCON 15-16 [1]
STM_CMPx 15-15 [1]
STM_ICR 15-18 [1]
STM_ID 15-10 [1]
STM_ISRR 15-20 [1]
STM_SRCx 15-21 [1]
STM_TIM0 15-11 [1]
STM_TIM1 15-11 [1]
STM_TIM2 15-12 [1]
STM_TIM3 15-12 [1]
STM_TIM4 15-12 [1]
STM_TIM5 15-13 [1]
STM_TIM6 15-13 [1]
Resolutions and ranges 15-4 [1]
T
Temperature compensation 5-41 [1]
Block diagram 5-42 [1]
Registers
SCU_TCCLR1 5-47 [1]
SCU_TCCON 5-44 [1]
SCU_TCLR0 5-46 [1]
Switching thresholds 5-43 [1]
TTCAN, see “CAN”
W
Watchdog timer 16-1 [1]–??
During power-saving modes 16-17 [1]
Endinit function 16-3 [1]
Features 16-2 [1]
Functional description 16-5 [1]
in OCDS suspend mode 16-17 [1]
Modify access to WDT_CON0
16-11 [1]
Monitoring diagram 16-26 [1]
Operating modes 16-7 [1]
Disable mode 16-8 [1], 16-15 [1]
Normal mode 16-8 [1], 16-14 [1]
Prewarning mode 16-9 [1],
16-16 [1]
Time-out mode 16-8 [1], 16-13 [1]
Operation sequence example 16-5 [1]
Overview 16-1 [1]
Period calculation 16-18 [1]
Period in power-saving modes
16-21 [1]
Registers 16-28 [1]
Offset addresses 16-28 [1]
WDT_CON0 16-29 [1]
WDT_CON1 16-31 [1]
WDT_SR 16-32 [1]
Service sequence diagram 16-25 [1]
Servicing 16-23 [1]
System initialization 16-22 [1]
Time-out period 16-18 [1]
WDT, see “Watchdog timer”
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