Debug/Suspend Mode
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SPNU563A–March 2018
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Controller Area Network (DCAN) Module
27.16 Debug/Suspend Mode
When the CPU is halted during debug, all DCAN registers are visible and can be inspected and modified
by the CPU.
In addition, the Message RAM is directly memory-mapped as described in Table 27-3.
The CAN controller provides two options for entering the debug/suspend state. The options are controlled
by the IDS bit in the CAN Control Register (DCAN CTL). By default, when IDS is 0, the DCAN controller
completes any active transfers on the CAN bus and waits until the bus is idle before halting. When IDS is
1, the DCAN halts immediately as soon as the CPU is halted.
The InitDbg bit in DCAN CTL register indicates when the DCAN controller has actually entered the
debug/suspend state.
NOTE: During Debug/Suspend Mode, the Message RAM cannot be accessed via the IFx register
sets.
Writing to control registers in debug/suspend mode may influence the CAN state machine
and further message handling.
For debug support, the auto clear functionality of the following DCAN registers is disabled:
• Error and Status Register (clear of status flags by read)
• IF1/IF2 Command Registers (clear of DMAActive flag by read/write)
27.17 DCAN Control Registers
Table 27-6 lists the control registers of the DCAN. After hardware reset, the registers of the DCAN hold
the values shown in the register descriptions. The base address for the control registers is FFF7 DC00h
for DCAN1, FFF7 DE00h for DCAN2, FFF7 E000h for DCAN3, and FFF7 E200h for DCAN4.
Additionally, the Bus-Off state is reset and the CAN_TX pin is set to recessive (HIGH). The Init bit in the
CAN Control Register is set to enable the software initialization. The DCAN will not influence the CAN bus
until the CPU resets Init to 0.
Table 27-6. DCAN Control Registers
Offset Acronym Register Description Section
00h DCAN CTL CAN Control Register Section 27.17.1
04h DCAN ES Error and Status Register Section 27.17.2
08h DCAN ERRC Error Counter Register Section 27.17.3
0Ch DCAN BTR Bit Timing Register Section 27.17.4
10h DCAN INT Interrupt Register Section 27.17.5
14h DCAN TEST Test Register Section 27.17.6
1Ch DCAN PERR Parity Error Code Register Section 27.17.7
20h DCAN REL Core Release Register Section 27.17.8
24h DCAN ECCDIAG ECC Diagnostic Register Section 27.17.9
28h DCAN ECCDIAG STAT ECC Diagnostic Status Register Section 27.17.10
2Ch DCAN ECC CS ECC Control and Status Register Section 27.17.11
30h DCAN ECC SERR ECC Single-Bit Error Code Register Section 27.17.12
80h DCAN ABOTR Auto-Bus-On Time Register Section 27.17.13
84h DCAN TXRQX Transmission Request X Register Section 27.17.14
88h DCAN TXRQ12 Transmission Request 12 Register Section 27.17.15
8Ch DCAN TXRQ34 Transmission Request 34 Register Section 27.17.15
90h DCAN TXRQ56 Transmission Request 56 Register Section 27.17.15
94h DCAN TXRQ78 Transmission Request 78 Register Section 27.17.15
98h DCAN NWDATX New Data X Register Section 27.17.16
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