Texas Instruments TMS570LC4357 - Page 42

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SPNU563A–March 2018
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List of Figures
17-47. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h]..................................................... 623
17-48. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h]..................................................... 623
17-49. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h]..................................................... 624
17-50. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh] .................................................... 624
18-1. CRC Controller Block Diagram For One Channel.................................................................... 627
18-2. Linear Feedback Shift Register (LFSR)................................................................................ 629
18-3. AUTO Mode Using Hardware Timer Trigger.......................................................................... 632
18-4. AUTO Mode With Software CPU Trigger.............................................................................. 632
18-5. Semi-CPU Mode With Hardware Timer Trigger ...................................................................... 633
18-6. Timeout Example 1....................................................................................................... 635
18-7. Timeout Example 2....................................................................................................... 636
18-8. Timeout Example 3....................................................................................................... 636
18-9. CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h] ...................................................... 642
18-10. CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h] ...................................................... 642
18-11. CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h] ...................................................... 643
18-12. CRC Interrupt Enable Set Register (CRC_INTS) [offset = 18h] .................................................... 644
18-13. CRC Interrupt Enable Reset Register (CRC_INTR) [offset = 20h]................................................. 646
18-14. CRC Interrupt Status Register (CRC_STATUS) [offset = 28h] ..................................................... 648
18-15. CRC Interrupt Offset (CRC_INT_OFFSET_REG) [offset = 30h] ................................................... 650
18-16. CRC Busy Register (CRC_BUSY) [offset = 38h]..................................................................... 651
18-17. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) [offset = 40h] .............................. 651
18-18. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) [offset = 44h] ............................... 652
18-19. CRC Current Sector Preload Register 1 (CRC_CURSEC_REG1) [offset = 48h] ................................ 652
18-20. CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) [offset = 4Ch] .................. 653
18-21. CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1) [offset = 50h]............. 653
18-22. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h] ....................................... 654
18-23. Channel 1 PSA Signature High Register (PSA_SIGREGH1) [offset = 64h] ...................................... 654
18-24. Channel 1 CRC Value Low Register (CRC_REGL1) [offset = 68h]................................................ 654
18-25. Channel 1 CRC Value High Register (CRC_REGH1) [offset = 6Ch] .............................................. 655
18-26. Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) [offset = 70h] ......................... 655
18-27. Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) [offset = 74h] ........................ 655
18-28. Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h].......................................... 656
18-29. Channel 1 Raw Data High Register (RAW_DATAREGH1) [offset = 7Ch] ........................................ 656
18-30. CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) [offset = 80h] .............................. 656
18-31. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) [offset = 84h] ............................... 657
18-32. CRC Current Sector Register 2 (CRC_CURSEC_REG2) [offset = 88h] .......................................... 657
18-33. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) [offset = 8Ch] .................. 658
18-34. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2) [offset = 90h]............. 658
18-35. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h]....................................... 659
18-36. Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h]...................................... 659
18-37. Channel 2 CRC Value Low Register (CRC_REGL2) [offset = A8h] ............................................... 659
18-38. Channel 2 CRC Value High Register (CRC_REGH2) [offset = ACh].............................................. 660
18-39. Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) [offset = B0h]......................... 660
18-40. Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) [offset = B4h]........................ 660
18-41. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h] ......................................... 661
18-42. Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh]........................................ 661
19-1. Block Diagram of Dual VIM for Safety Support....................................................................... 664
19-2. Device Level Interrupt Block Diagram ................................................................................. 665
19-3. VIM Interrupt Handling Block Diagram................................................................................. 668