User’s Manual L-6 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Configuration word 13-23 [1]
Emulation mode 13-20 [1]
External boot mode 13-21 [1]
Start-up modes 13-20 [1]
Burst Flash
Application configurations
13-66 [1], 13-67 [1]
Burst read timing 13-74 [1],
13-75 [1]
Clock input BFCLKI 13-72 [1]
Clock output BFCLKO 13-71 [1]
Cycle termination 13-78 [1]
Signals 13-65 [1]
Wait control 13-75 [1]
Chip select override mode 13-34 [1]
Data re-alignment 13-37 [1]
External bus arbitration 13-7 [1]
Arbitration modes 13-10 [1]
Arbitration signals 13-7 [1]
Arbitration timing 13-11 [1]
EBU as participant 13-14 [1]
EBU as sole master 13-10 [1]
Locking external bus 13-17 [1]
Modes 13-7 [1]
PLMB access to external bus
13-18 [1]
Interfacing INTEL-style devices
13-61 [1]
Interfacing MOTOROLA-style devices
13-63 [1]
Memory regions 13-26 [1]
Registers
ADDRSELx 13-90 [1]
BFCON 13-86 [1]
BUSAPx 13-97 [1]
BUSCONx 13-92 [1]
CLC 13-82 [1]
CON 13-83 [1]
EMUAS 13-101 [1]
EMUBAP 13-106 [1]
EMUBC 13-102 [1]
EMUOVL 13-110 [1]
ID 13-81 [1]
Overview 13-79 [1]
USERCON 13-111 [1]
EBU, see “External bus interface unit”
EEPROM emulation 7-26 [1]
Emergency stop output control 5-57 [1]
for GPTA 5-58 [1]
Register SCU_EMSR 5-59 [1]
Entering Sleep Mode 5-6 [1]
Error correction in Flash 7-34 [1]
External bus interface unit, see “EBU”
External request unit 5-9 [1]
Block diagram 5-9 [1]
Features 5-9 [1]
Implementation 5-14 [1]
Interrupt gating logic 5-12 [1]
Registers 5-16 [1]
EICR0 5-17 [1]
EICR1 5-20 [1]
EIFR 5-23 [1]
FMR 5-24 [1]
IGCR0 5-26 [1]
IGCR1 5-29 [1]
Overview 5-16 [1]
PDDR 5-25 [1]
TGADC0 5-32 [1]
TGADC1 5-32 [1]
TGADCx 25-116 [2]
Request select logic 5-10 [1]
F
FADC
Analog inputs 26-4 [2]
Calibration 26-22 [2]
Channel timers 26-11 [2]
Channel triggers 26-9 [2]
Clock generation 26-13 [2]
Conversion priority 26-12 [2]
Data reduction filter 26-13 [2]
Features 26-2 [2]
Filter block structure 26-15 [2]
Filter concatenation 26-19 [2]
Gating modes 26-10 [2]
Interrupts 26-24 [2]
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