Infineon Technologies TC1796 - Page 2121

User’s Manual L-5 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Move engine interrupts 12-30 [1]
Transaction lost interrupts 12-29 [1]
Wrap buffer interrupts 12-32 [1]
Pattern detection 12-34 [1]
Principle 12-5 [1]
Registers
ADRCRmx 12-83 [1]
Block address map 12-109 [1]
CHCRmx 12-76 [1]
CHICRmx 12-81 [1]
CHRSTR 12-51 [1]
CHSRmx 12-80 [1]
CLRE 12-62 [1]
DADRmx 12-89 [1]
EER 12-56 [1]
ERRSR 12-59 [1]
GINTR 12-50 [1]
HTREQ 12-55 [1]
ID 12-45 [1]
INTCR 12-67 [1]
INTSR 12-64 [1]
MEmAENR 12-73 [1]
MEmARR 12-74 [1]
MEmPR 12-72 [1]
MEmR 12-71 [1]
MESR 12-69 [1]
OCDSR 12-46 [1]
Offset addresses 12-43 [1]
Overview 12-42 [1]
SADRmx 12-88 [1]
SHADRmx 12-90 [1]
STREQ 12-54 [1]
SUSPMR 12-48 [1]
TRSR 12-52 [1]
WRPSR 12-66 [1]
Request wiring matrix 12-91 [1]
Transaction control 12-20 [1]
DMI
Dual-ported RAM 2-32 [1]
Features 2-31 [1]
Registers
DMI_ATR 2-39 [1]
DMI_CON 2-36 [1]
DMI_CON1 2-37 [1]
DMI_STR 2-38 [1]
DMU
Access performance 8-7 [1]
Block diagram 8-1 [1]
Data access overlay operation 8-3 [1]
Data access redirection 8-4 [1]
Emulation memory overlay 8-7 [1]
Registers 8-10 [1]
ID 8-11 [1]
OMASKx 8-16 [1]
OTARx 8-15 [1]
RABRx 8-13 [1]
SBRCTR 8-12 [1]
SBRAM 8-2 [1]
SRAM 8-2 [1]
Document
Structure 1-1 [1]
Terminology and abbreviations 1-3 [1]
Textual conventions 1-1 [1]
E
EBU 13-1 [1]
Access parameter selection 13-35 [1]
Access phases 13-41 [1]
Address phase 13-41 [1]
Burst phase 13-46 [1]
Command delay phase 13-43 [1]
Command phase 13-43 [1]
Data hold phase 13-45 [1]
Recovery phase 13-47 [1]
Address region selection 13-31 [1]
Asynchronous accesses
Demultiplexed device configura-
tions 13-51 [1]
Demultiplexed read cycles
13-55 [1]
Demultiplexed write cycles
13-56 [1]
Signals 13-50 [1]
Wait control 13-57 [1]
Boot operation 13-20 [1]
Boot read access cycle 13-22 [1]