Infineon Technologies TC1796 - Page 2120

User’s Manual L-4 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
REFMR 22-161 [2]
SISR 22-195 [2]
STPTR0 22-192 [2]
STSRH 22-194 [2]
STSRL 22-193 [2]
SYNMR 22-160 [2]
TTCFGR 22-173 [2]
TTCR 22-169 [2]
TTFMR 22-180 [2]
TTIER 22-186 [2]
TTINPR 22-190 [2]
TTIRR 22-182 [2]
TTSR 22-175 [2]
TURR 22-157 [2]
Chip select outputs 13-28 [1]
CLC register 3-24 [1]
Implementation in the modules 3-39 [1]
Clock system
CGU block diagram 3-3 [1]
Clock source 3-10 [1]
Clock tree diagram 3-2 [1]
Features 3-1 [1]
Gain control 3-7 [1]
Main oscillator 3-4 [1]
Main oscillator circuits 3-5 [1]
Module clock generation 3-23 [1]
CLC register 3-24 [1]
Fractional divider 3-29 [1]
OSC_CON register 3-8 [1]
Oscillator run detection 3-6 [1]
Overview 3-1 [1]
Configuration inputs 5-8 [1]
Register 10-24 [1]
CPS
Registers
CPU_SBSRC 2-19 [1]
CPU_SRCn 2-14 [1]
CPU
Block diagram 2-3 [1]
Execution unit 2-5 [1]
Features 2-2 [1]
General purpose register file 2-6 [1]
Implementation-specific features
2-2 [1]
Instruction fetch unit 2-4 [1]
Registers 2-9 [1]
Core debug registers 2-17 [1]
CPS registers 2-13 [1]
CPU_SRCn 2-14 [1]
CSFRs 2-10 [1]
GPRs 2-15 [1]
Memory protection registers
2-20 [1]
MMU_CON 2-12 [1]
PSW 2-11 [1]
SBSRC0 2-19 [1]
TRnEVT 2-18 [1]
CPU, see also Processor subsystem
CSCOMB control 13-28 [1]
CSFR registers 2-10 [1]
D
Dedicated peripheral I/O lines 10-83 [1]
for MSC0 and MSC1 10-85 [1]
for SSC0 and SSC1 10-83 [1]
Die temperature sensor 5-48 [1],
25-120 [2]
DMA 12-2 [1]
Access protection 12-40 [1]
Access protection assignment
12-98 [1]
Block diagram 12-2 [1]
Bus bandwidth allocation 12-22 [1]
Bus switch 12-21 [1]
Channel operation 12-6 [1]
Channel operation modes 12-11 [1]
Channel request control 12-10 [1]
Channel reset operation 12-16 [1]
Circular buffer 12-19 [1]
Debug capabilities 12-23 [1]
Definition of terms 12-4 [1]
Error conditions 12-15 [1]
Features 12-3 [1]
Implementation diagram 12-91 [1]
Interrupts 12-27 [1]
Channel interrupts 12-27 [1]