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SCI Control Registers
1733
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
30.7 SCI Control Registers
These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI is controlled and accessed
through the registers listed in Table 30-3. Among the features that can be programmed are the SCI
communication and timing modes, baud rate value, frame format, DMA requests, and interrupt
configuration. The base address for the control registers is FFF7 E500h for SCI3 and FFF7 E700h for
SCI4.
Table 30-3. SCI Control Registers Summary
Offset Acronym Register Description Section
00h SCIGCR0 SCI Global Control Register 0 Section 30.7.1
04h SCIGCR1 SCI Global Control Register 1 Section 30.7.2
0Ch SCISETINT SCI Set Interrupt Register Section 30.7.3
10h SCICLEARINT SCI Clear Interrupt Register Section 30.7.4
14h SCISETINTLVL SCI Set Interrupt Level Register Section 30.7.5
18h SCICLEARINTLVL SCI Clear Interrupt Level Register Section 30.7.6
1Ch SCIFLR SCI Flags Register Section 30.7.7
20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Section 30.7.8
24h SCIINTVECT1 SCI Interrupt Vector Offset 1 Section 30.7.9
28h SCIFORMAT SCI Format Control Register Section 30.7.10
2Ch BRS Baud Rate Selection Register Section 30.7.11
30h SCIED Receiver Emulation Data Buffer Section 30.7.12.1
34h SCIRD Receiver Data Buffer Section 30.7.12.2
38h SCITD Transmit Data Buffer Section 30.7.12.3
3Ch SCIPIO0 SCI Pin I/O Control Register 0 Section 30.7.13
40h SCIPIO1 SCI Pin I/O Control Register 1 Section 30.7.14
44h SCIPIO2 SCI Pin I/O Control Register 2 Section 30.7.15
48h SCIPIO3 SCI Pin I/O Control Register 3 Section 30.7.16
4Ch SCIPIO4 SCI Pin I/O Control Register 4 Section 30.7.17
50h SCIPIO5 SCI Pin I/O Control Register 5 Section 30.7.18
54h SCIPIO6 SCI Pin I/O Control Register 6 Section 30.7.19
58h SCIPIO7 SCI Pin I/O Control Register 7 Section 30.7.20
5Ch SCIPIO8 SCI Pin I/O Control Register 8 Section 30.7.21
90h IODFTCTRL Input/Output Error Enable Register Section 30.7.22
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