TC1796
System and Peripheral Units (Vol. 1 and 2)
User’s Manual V2.0, 2007-07
12-99 Address range for AEN21 is updated.
12-111,
12-112
MCHK_ID is added.
13-3 Section 13.2.1 is updated.
13-24 CONF32BIT description is updated.
13-72 BFCLKO configurations in Figure 13-27 are updated.
13-75 Burst Flash Read Cycle diagram in Figure 13-29 is added.
13-79, 13-81 EBU_ID is added.
14-13 NMI trap handler in Figure 14.5 is updated.
15-7, 15-8,
15-10
STM_ID is added.
18-16 Access modes in Table 18-7 are updated.
18-122 DBCU register adresses in Table 18-38 are updated.
Volume 2: Peripheral Units
19-19, 19-20 ASC0_ID and ASC1_ID register are added.
20-21 Note in Figure 20-11 corrected; TB write operation in
Section 20.1.2.11 is updated.
20-24, 20-31,
20-33
SSC error interrupt control in Section 20.1.2.12 and bit description
STIP, EN are updated.
20-27, 20-29 SSC0_ID and SSC1_ID registers are added.
20-37, 20-39, Notes below register SSOC and SSOTC are updated.
21-26 Figure 21-18 is updated (sampling start).
21-36, 21-38 MSC0_ID and MSC1_ID registers are added.
21-42 Bit description of NDBH is updated.
21-21, 21-25,
21-66
Values for baud rate selections corrected at several locations and
equations.
22-53 Usage of bit RXEN in Section 22.3.11.5 is updated.
22-54 First paragraph of Section 22.3.11.6 is updated.
22-59 Offset addresses for registers MSIMASK, PANCTR, MCR, and MITR in
Table 22-5 corrected.
TC1796 User’s Manual
Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units
Revision History: V2.0, 2007-07
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