Texas Instruments TMS570LC4357 - Page 21

www.ti.com
21
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Contents
27.8.11 Storing Received Messages in FIFO Buffers ............................................................ 1441
27.8.12 Reading from a FIFO Buffer............................................................................... 1441
27.9 CAN Message Transfer ................................................................................................ 1443
27.9.1 Automatic Retransmission ................................................................................... 1443
27.9.2 Auto-Bus-On ................................................................................................... 1444
27.10 Interrupt Functionality .................................................................................................. 1444
27.10.1 Message Object Interrupts ................................................................................. 1444
27.10.2 Status Change Interrupts ................................................................................... 1445
27.10.3 Error Interrupts ............................................................................................... 1445
27.11 Global Power Down Mode............................................................................................. 1446
27.11.1 Entering Global Power Down Mode....................................................................... 1446
27.11.2 Wakeup From Global Power Down Mode................................................................ 1446
27.12 Local Power Down Mode .............................................................................................. 1447
27.12.1 Entering Local Power Down Mode ........................................................................ 1447
27.12.2 Wakeup From Local Power Down......................................................................... 1447
27.13 GIO Support ............................................................................................................. 1447
27.14 Test Modes .............................................................................................................. 1449
27.14.1 Silent Mode................................................................................................... 1449
27.14.2 Loop Back Mode............................................................................................. 1450
27.14.3 External Loop Back Mode .................................................................................. 1451
27.14.4 Loop Back Combined with Silent Mode................................................................... 1452
27.14.5 Software Control of CAN_TX Pin.......................................................................... 1452
27.15 SECDED Mechanism................................................................................................... 1453
27.15.1 Behavior on Single-Bit Error................................................................................ 1453
27.15.2 Behavior on Double-Bit Error............................................................................... 1453
27.15.3 SECDED Testing ............................................................................................ 1453
27.16 Debug/Suspend Mode.................................................................................................. 1454
27.17 DCAN Control Registers ............................................................................................... 1454
27.17.1 CAN Control Register (DCAN CTL) ....................................................................... 1456
27.17.2 Error and Status Register (DCAN ES).................................................................... 1459
27.17.3 Error Counter Register (DCAN ERRC) ................................................................... 1461
27.17.4 Bit Timing Register (DCAN BTR).......................................................................... 1462
27.17.5 Interrupt Register (DCAN INT)............................................................................. 1463
27.17.6 Test Register (DCAN TEST) ............................................................................... 1464
27.17.7 Parity Error Code Register (DCAN PERR)............................................................... 1465
27.17.8 Core Release Register (DCAN REL) ..................................................................... 1465
27.17.9 ECC Diagnostic Register (DCAN ECCDIAG)............................................................ 1466
27.17.10 ECC Diagnostic Status Register (DCAN ECCDIAG STAT) .......................................... 1466
27.17.11 ECC Control and Status Register (DCAN ECC CS)................................................... 1467
27.17.12 ECC Single-Bit Error Code Register (DCAN ECC SERR)............................................ 1468
27.17.13 Auto-Bus-On Time Register (DCAN ABOTR) .......................................................... 1469
27.17.14 Transmission Request X Register (DCAN TXRQ X) .................................................. 1469
27.17.15 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ............................ 1470
27.17.16 New Data X Register (DCAN NWDAT X)............................................................... 1471
27.17.17 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ...................................... 1472
27.17.18 Interrupt Pending X Register (DCAN INTPND X)...................................................... 1473
27.17.19 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) ............................. 1474
27.17.20 Message Valid X Register (DCAN MSGVAL X)........................................................ 1475
27.17.21 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78).............................. 1476
27.17.22 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78).......................... 1477
27.17.23 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)..................................... 1478
27.17.24 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) ........................................... 1481
27.17.25 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)...................................... 1482