Texas Instruments TMS570LC4357 - Page 22

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22
SPNU563A–March 2018
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Contents
27.17.26 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) .......................... 1484
27.17.27 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) ........ 1486
27.17.28 IF3 Observation Register (DCAN IF3OBS)............................................................. 1487
27.17.29 IF3 Mask Register (DCAN IF3MSK)..................................................................... 1489
27.17.30 IF3 Arbitration Register (DCAN IF3ARB) ............................................................... 1490
27.17.31 IF3 Message Control Register (DCAN IF3MCTL) ..................................................... 1491
27.17.32 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB) .......................................... 1492
27.17.33 IF3 Update Enable Registers (DCAN IF3UPD12 to DCAN IF3UPD78) ............................ 1493
27.17.34 CAN TX IO Control Register (DCAN TIOC) ............................................................ 1494
27.17.35 CAN RX IO Control Register (DCAN RIOC)............................................................ 1495
28 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP). 1497
28.1 Overview.................................................................................................................. 1498
28.1.1 Features ........................................................................................................ 1498
28.1.2 Pin Configurations............................................................................................. 1499
28.1.3 MibSPI /SPI Configurations.................................................................................. 1500
28.2 Basic Operation.......................................................................................................... 1500
28.2.1 SPI Mode....................................................................................................... 1500
28.2.2 MibSPI Mode .................................................................................................. 1502
28.2.3 DMA Requests ................................................................................................ 1503
28.2.4 Interrupts ....................................................................................................... 1505
28.2.5 Physical Interface ............................................................................................. 1507
28.2.6 Advanced Module Configuration Options .................................................................. 1511
28.2.7 General-Purpose I/O.......................................................................................... 1529
28.2.8 Low-Power Mode.............................................................................................. 1529
28.2.9 Safety Features................................................................................................ 1529
28.2.10 Test Features ................................................................................................ 1531
28.2.11 Module Configuration ....................................................................................... 1533
28.3 Control Registers........................................................................................................ 1535
28.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1536
28.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1537
28.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1538
28.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1540
28.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1541
28.3.6 SPI Pin Control Register 0 (SPIPC0)....................................................................... 1544
28.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1545
28.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1547
28.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1548
28.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1549
28.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1551
28.3.12 SPI Pin Control Register 6 (SPIPC6) ..................................................................... 1552
28.3.13 SPI Pin Control Register 7 (SPIPC7) ..................................................................... 1554
28.3.14 SPI Pin Control Register 8 (SPIPC8) ..................................................................... 1555
28.3.15 SPI Transmit Data Register 0 (SPIDAT0) ................................................................ 1556
28.3.16 SPI Transmit Data Register 1 (SPIDAT1) ................................................................ 1557
28.3.17 SPI Receive Buffer Register (SPIBUF) ................................................................... 1560
28.3.18 SPI Emulation Register (SPIEMU) ........................................................................ 1562
28.3.19 SPI Delay Register (SPIDELAY) .......................................................................... 1562
28.3.20 SPI Default Chip Select Register (SPIDEF).............................................................. 1565
28.3.21 SPI Data Format Registers (SPIFMT[3:0]) ............................................................... 1566
28.3.22 Interrupt Vector 0 (INTVECT0)............................................................................. 1568
28.3.23 Interrupt Vector 1 (INTVECT1)............................................................................. 1569
28.3.24 SPI Pin Control Register 9 (SPIPC9) ..................................................................... 1571
28.3.25 Parallel/Modulo Mode Control Register (SPIPMCTRL)................................................. 1572