Texas Instruments TMS570LC4357

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23
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
28.3.26 Multi-buffer Mode Enable Register (MIBSPIE)........................................................... 1575
28.3.27 TG Interrupt Enable Set Register (TGITENST).......................................................... 1576
28.3.28 TG Interrupt Enable Clear Register (TGITENCR)....................................................... 1577
28.3.29 Transfer Group Interrupt Level Set Register (TGITLVST).............................................. 1578
28.3.30 Transfer Group Interrupt Level Clear Register (TGITLVCR)........................................... 1579
28.3.31 Transfer Group Interrupt Flag Register (TGINTFLAG) ................................................. 1580
28.3.32 Tick Count Register (TICKCNT) ........................................................................... 1581
28.3.33 Last TG End Pointer (LTGPEND) ......................................................................... 1582
28.3.34 TGx Control Registers (TGxCTRL)........................................................................ 1583
28.3.35 DMA Channel Control Register (DMAxCTRL) ........................................................... 1586
28.3.36 DMAxCOUNT Register (ICOUNT) ........................................................................ 1588
28.3.37 DMA Large Count (DMACNTLEN) ........................................................................ 1589
28.3.38 Parity/ECC Control Register (PAR_ECC_CTRL)........................................................ 1590
28.3.39 Parity/ECC Status Register (PAR_ECC_STAT)......................................................... 1591
28.3.40 Uncorrectable Parity or Double-Bit ECC Error Address Register - RXRAM (UERRADDR1)...... 1592
28.3.41 Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM (UERRADDR0)...... 1594
28.3.42 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) ................................. 1595
28.3.43 I/O-Loopback Test Control Register (IOLPBKTSTCR) ................................................. 1596
28.3.44 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1).... 1598
28.3.45 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3).... 1600
28.3.46 ECC Diagnostic Control Register (ECCDIAG_CTRL) .................................................. 1601
28.3.47 ECC Diagnostic Status Register (ECCDIAG_STAT) ................................................... 1602
28.3.48 Single-Bit Error Address Register - RXRAM (SBERRADDR1) ........................................ 1603
28.3.49 Single-Bit Error Address Register - TXRAM (SBERRADDR0) ........................................ 1604
28.4 Multi-buffer RAM ........................................................................................................ 1605
28.4.1 Multi-buffer RAM Auto Initialization ......................................................................... 1606
28.4.2 Multi-buffer RAM Register Summary ....................................................................... 1606
28.4.3 Multi-buffer RAM Transmit Data Register (TXRAM)...................................................... 1607
28.4.4 Multi-buffer RAM Receive Buffer Register (RXRAM)..................................................... 1610
28.5 Parity\ECC Memory..................................................................................................... 1612
28.5.1 Example of Parity Memory Organization................................................................... 1615
28.5.2 Example of ECC Memory Organization .................................................................... 1616
28.6 MibSPI Pin Timing Parameters........................................................................................ 1617
28.6.1 Master Mode Timings for SPI/MibSPI ...................................................................... 1617
28.6.2 Slave Mode Timings for SPI/MibSPI........................................................................ 1619
28.6.3 Master Mode Timing Parameter Details.................................................................... 1620
28.6.4 Slave Mode Timing Parameter Details ..................................................................... 1620
29 Serial Communication Interface (SCI)/ Local Interconnect Network (LIN) Module.................... 1621
29.1 Introduction and Features.............................................................................................. 1622
29.1.1 SCI Features................................................................................................... 1622
29.1.2 LIN Features ................................................................................................... 1623
29.1.3 Block Diagram ................................................................................................. 1624
29.2 SCI ........................................................................................................................ 1627
29.2.1 SCI Communication Formats................................................................................ 1627
29.2.2 SCI Interrupts .................................................................................................. 1635
29.2.3 SCI DMA Interface ............................................................................................ 1638
29.2.4 SCI Configurations ............................................................................................ 1639
29.2.5 SCI Low-Power Mode ........................................................................................ 1641
29.3 LIN......................................................................................................................... 1642
29.3.1 LIN Communication Formats ................................................................................ 1642
29.3.2 LIN Interrupts .................................................................................................. 1659
29.3.3 LIN DMA Interface ............................................................................................ 1659
29.3.4 LIN Configurations ............................................................................................ 1660