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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
29.4 Low-Power Mode........................................................................................................ 1662
29.4.1 Entering Sleep Mode ......................................................................................... 1662
29.4.2 Wakeup......................................................................................................... 1663
29.4.3 Wakeup Timeouts............................................................................................. 1664
29.5 Emulation Mode ......................................................................................................... 1664
29.6 GPIO Functionality ...................................................................................................... 1665
29.6.1 GPIO Functionality ............................................................................................ 1665
29.6.2 Under Reset ................................................................................................... 1665
29.6.3 Out of Reset ................................................................................................... 1666
29.6.4 Open-Drain Feature Enabled on a Pin ..................................................................... 1666
29.6.5 Summary ....................................................................................................... 1666
29.7 SCI/LIN Control Registers.............................................................................................. 1667
29.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................ 1668
29.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................ 1669
29.7.3 SCI Global Control Register 2 (SCIGCR2) ................................................................ 1673
29.7.4 SCI Set Interrupt Register (SCISETINT)................................................................... 1675
29.7.5 SCI Clear Interrupt Register (SCICLEARINT)............................................................. 1678
29.7.6 SCI Set Interrupt Level Register (SCISETINTLVL)....................................................... 1681
29.7.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL)................................................. 1684
29.7.8 SCI Flags Register (SCIFLR)................................................................................ 1687
29.7.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ............................................................ 1694
29.7.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1)........................................................... 1694
29.7.11 SCI Format Control Register (SCIFORMAT) ............................................................ 1695
29.7.12 Baud Rate Selection Register (BRS) ..................................................................... 1696
29.7.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................. 1698
29.7.14 SCI Pin I/O Control Register 0 (SCIPIO0) ............................................................... 1699
29.7.15 SCI Pin I/O Control Register 1 (SCIPIO1) ............................................................... 1700
29.7.16 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................... 1701
29.7.17 SCI Pin I/O Control Register 3 (SCIPIO3) ............................................................... 1702
29.7.18 SCI Pin I/O Control Register 4 (SCIPIO4) ............................................................... 1703
29.7.19 SCI Pin I/O Control Register 5 (SCIPIO5) ............................................................... 1704
29.7.20 SCI Pin I/O Control Register 6 (SCIPIO6) ............................................................... 1705
29.7.21 SCI Pin I/O Control Register 7 (SCIPIO7) ............................................................... 1706
29.7.22 SCI Pin I/O Control Register 8 (SCIPIO8) ............................................................... 1707
29.7.23 LIN Compare Register (LINCOMPARE).................................................................. 1708
29.7.24 LIN Receive Buffer 0 Register (LINRD0) ................................................................. 1709
29.7.25 LIN Receive Buffer 1 Register (LINRD1) ................................................................. 1710
29.7.26 LIN Mask Register (LINMASK) ............................................................................ 1711
29.7.27 LIN Identification Register (LINID)......................................................................... 1712
29.7.28 LIN Transmit Buffer 0 Register (LINTD0)................................................................. 1713
29.7.29 LIN Transmit Buffer 1 Register (LINTD1)................................................................. 1713
29.7.30 Maximum Baud Rate Selection Register (MBRS)....................................................... 1714
29.7.31 Input/Output Error Enable (IODFTCTRL) Register...................................................... 1715
30 Serial Communication Interface (SCI) Module..................................................................... 1717
30.1 Introduction............................................................................................................... 1718
30.1.1 SCI Features................................................................................................... 1718
30.1.2 Block Diagram ................................................................................................. 1718
30.2 SCI Communication Formats .......................................................................................... 1720
30.2.1 SCI Frame Formats........................................................................................... 1720
30.2.2 SCI Timing Mode.............................................................................................. 1721
30.2.3 SCI Baud Rate................................................................................................. 1722
30.2.4 SCI Multiprocessor Communication Modes ............................................................... 1722
30.3 SCI Interrupts ............................................................................................................ 1725
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