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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
30.3.1 Transmit Interrupt ............................................................................................. 1726
30.3.2 Receive Interrupt .............................................................................................. 1726
30.3.3 WakeUp Interrupt ............................................................................................. 1726
30.3.4 Error Interrupts ................................................................................................ 1727
30.4 SCI DMA Interface ...................................................................................................... 1728
30.4.1 Receive DMA Requests...................................................................................... 1728
30.4.2 Transmit DMA Requests ..................................................................................... 1729
30.5 SCI Configurations ...................................................................................................... 1729
30.5.1 Receiving Data ................................................................................................ 1730
30.5.2 Transmitting Data ............................................................................................. 1730
30.6 SCI Low-Power Mode .................................................................................................. 1731
30.6.1 Sleep Mode for Multiprocessor Communication .......................................................... 1732
30.7 SCI Control Registers .................................................................................................. 1733
30.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................ 1734
30.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................ 1735
30.7.3 SCI Set Interrupt Register (SCISETINT) .................................................................. 1738
30.7.4 SCI Clear Interrupt Register (SCICLEARINT) ............................................................ 1740
30.7.5 SCI Set Interrupt Level Register (SCISETINTLVL) ...................................................... 1742
30.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ................................................ 1743
30.7.7 SCI Flags Register (SCIFLR) ............................................................................... 1745
30.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ........................................................... 1749
30.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ........................................................... 1749
30.7.10 SCI Format Control Register (SCIFORMAT) ............................................................ 1750
30.7.11 Baud Rate Selection Register (BRS) ..................................................................... 1751
30.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................. 1752
30.7.13 SCI Pin I/O Control Register 0 (SCIPIO0) ............................................................... 1753
30.7.14 SCI Pin I/O Control Register 1 (SCIPIO1) ............................................................... 1754
30.7.15 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................... 1755
30.7.16 SCI Pin I/O Control Register 3 (SCIPIO3) ............................................................... 1756
30.7.17 SCI Pin I/O Control Register 4 (SCIPIO4) ............................................................... 1757
30.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) ............................................................... 1758
30.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) ............................................................... 1759
30.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) ............................................................... 1760
30.7.21 SCI Pin I/O Control Register 8 (SCIPIO8) ............................................................... 1760
30.7.22 Input/Output Error Enable (IODFTCTRL) Register ..................................................... 1761
30.8 GPIO Functionality ...................................................................................................... 1763
30.8.1 GPIO Functionality ............................................................................................ 1763
30.8.2 Under Reset ................................................................................................... 1763
30.8.3 Out of Reset ................................................................................................... 1764
30.8.4 Open-Drain Feature Enabled on a Pin ..................................................................... 1764
30.8.5 Summary ....................................................................................................... 1764
31 Inter-Integrated Circuit (I2C) Module.................................................................................. 1765
31.1 Overview.................................................................................................................. 1766
31.1.1 Introduction to the I2C Module .............................................................................. 1766
31.1.2 Functional Overview .......................................................................................... 1767
31.1.3 Clock Generation.............................................................................................. 1769
31.2 I2C Module Operation .................................................................................................. 1770
31.2.1 Input and Output Voltage Levels............................................................................ 1770
31.2.2 I2C Module Reset Conditions ............................................................................... 1770
31.2.3 I2C Module Data Validity .................................................................................... 1770
31.2.4 I2C Module Start and Stop Conditions ..................................................................... 1771
31.2.5 Serial Data Formats........................................................................................... 1771
31.2.6 NACK Bit Generation ......................................................................................... 1773
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