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26
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
31.3 I2C Operation Modes ................................................................................................... 1774
31.3.1 Master Transmitter Mode .................................................................................... 1774
31.3.2 Master Receiver Mode ....................................................................................... 1774
31.3.3 Slave Transmitter Mode...................................................................................... 1774
31.3.4 Slave Receiver Mode ........................................................................................ 1774
31.3.5 Low Power Mode.............................................................................................. 1775
31.3.6 Free Run Mode................................................................................................ 1775
31.3.7 Ignore NACK Mode .......................................................................................... 1775
31.4 I2C Module Integrity..................................................................................................... 1776
31.4.1 Arbitration ...................................................................................................... 1776
31.4.2 I2C Clock Generation and Synchronization ............................................................... 1777
31.4.3 Prescaler ....................................................................................................... 1777
31.4.4 Noise Filter ..................................................................................................... 1777
31.5 Operational Information................................................................................................. 1778
31.5.1 I2C Module Interrupts......................................................................................... 1778
31.5.2 DMA Controller Events ....................................................................................... 1779
31.5.3 I2C Enable/Disable............................................................................................ 1779
31.5.4 General Purpose I/O.......................................................................................... 1779
31.5.5 Pull Up/Pull Down Function.................................................................................. 1780
31.5.6 Open Drain Function.......................................................................................... 1780
31.6 I2C Control Registers................................................................................................... 1781
31.6.1 I2C Own Address Manager (I2COAR) ..................................................................... 1782
31.6.2 I2C Interrupt Mask Register (I2CIMR)...................................................................... 1783
31.6.3 I2C Status Register (I2CSTR) ............................................................................... 1784
31.6.4 I2C Clock Divider Low Register (I2CCKL) ................................................................. 1787
31.6.5 I2C Clock Control High Register (I2CCKH)................................................................ 1787
31.6.6 I2C Data Count Register (I2CCNT)......................................................................... 1788
31.6.7 I2C Data Receive Register (I2CDRR)...................................................................... 1788
31.6.8 I2C Slave Address Register (I2CSAR) ..................................................................... 1789
31.6.9 I2C Data Transmit Register (I2CDXR) ..................................................................... 1789
31.6.10 I2C Mode Register (I2CMDR).............................................................................. 1790
31.6.11 I2C Interrupt Vector Register (I2CIVR) ................................................................... 1793
31.6.12 I2C Extended Mode Register (I2CEMDR)................................................................ 1794
31.6.13 I2C Prescale Register (I2CPSC) .......................................................................... 1794
31.6.14 I2C Peripheral ID Register 1 (I2CPID1) .................................................................. 1795
31.6.15 I2C Peripheral ID Register 2 (I2CPID2) .................................................................. 1795
31.6.16 I2C DMA Control Register (I2CDMACR) ................................................................. 1796
31.6.17 I2C Pin Function Register (I2CPFNC) .................................................................... 1796
31.6.18 I2C Pin Direction Register (I2CPDIR)..................................................................... 1797
31.6.19 I2C Data Input Register (I2CDIN) ......................................................................... 1797
31.6.20 I2C Data Output Register (I2CDOUT) .................................................................... 1798
31.6.21 I2C Data Set Register (I2CDSET)......................................................................... 1798
31.6.22 I2C Data Clear Register (I2CDCLR) ...................................................................... 1799
31.6.23 I2C Pin Open Drain Register (I2CPDR) .................................................................. 1799
31.6.24 I2C Pull Disable Register (I2CPDIS)...................................................................... 1800
31.6.25 I2C Pull Select Register (I2CPSEL)....................................................................... 1800
31.6.26 I2C Pins Slew Rate Select Register (I2CSRS) .......................................................... 1801
31.7 Sample Waveforms ..................................................................................................... 1802
32 EMAC/MDIO Module ........................................................................................................ 1803
32.1 Introduction............................................................................................................... 1804
32.1.1 Purpose of the Peripheral.................................................................................... 1804
32.1.2 Features ........................................................................................................ 1804
32.1.3 Functional Block Diagram.................................................................................... 1805
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