Texas Instruments TMS570LC4357

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27
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
32.1.4 Industry Standard(s) Compliance Statement .............................................................. 1806
32.2 Architecture .............................................................................................................. 1806
32.2.1 Clock Control .................................................................................................. 1806
32.2.2 Memory Map................................................................................................... 1806
32.2.3 Signal Descriptions............................................................................................ 1807
32.2.4 MII / RMII Signal Multiplexing Control ...................................................................... 1810
32.2.5 Ethernet Protocol Overview.................................................................................. 1811
32.2.6 Programming Interface ....................................................................................... 1812
32.2.7 EMAC Control Module........................................................................................ 1827
32.2.8 MDIO Module .................................................................................................. 1828
32.2.9 EMAC Module ................................................................................................. 1833
32.2.10 MAC Interface................................................................................................ 1835
32.2.11 Packet Receive Operation.................................................................................. 1839
32.2.12 Packet Transmit Operation ................................................................................. 1844
32.2.13 Receive and Transmit Latency............................................................................. 1845
32.2.14 Transfer Node Priority....................................................................................... 1845
32.2.15 Reset Considerations ....................................................................................... 1846
32.2.16 Initialization ................................................................................................... 1847
32.2.17 Interrupt Support............................................................................................. 1849
32.2.18 Power Management ......................................................................................... 1853
32.2.19 Emulation Considerations .................................................................................. 1853
32.3 EMAC Control Module Registers...................................................................................... 1854
32.3.1 EMAC Control Module Revision ID Register (REVID) ................................................... 1855
32.3.2 EMAC Control Module Software Reset Register (SOFTRESET)....................................... 1855
32.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) .................................... 1856
32.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN) ....... 1857
32.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN) ............................... 1858
32.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN)............................... 1859
32.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN) ..................... 1860
32.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT) ..... 1861
32.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT) ............................. 1862
32.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT) ........................... 1863
32.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT) ................. 1864
32.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX)................ 1865
32.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX) ............... 1866
32.4 MDIO Registers.......................................................................................................... 1867
32.4.1 MDIO Revision ID Register (REVID) ....................................................................... 1867
32.4.2 MDIO Control Register (CONTROL) ....................................................................... 1868
32.4.3 PHY Acknowledge Status Register (ALIVE)............................................................... 1869
32.4.4 PHY Link Status Register (LINK) ........................................................................... 1869
32.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)........................... 1870
32.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ......................... 1871
32.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).................. 1872
32.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)................ 1873
32.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) .............. 1874
32.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)....... 1875
32.4.11 MDIO User Access Register 0 (USERACCESS0) ...................................................... 1876
32.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0).................................................. 1877
32.4.13 MDIO User Access Register 1 (USERACCESS1) ...................................................... 1878
32.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1).................................................. 1879
32.5 EMAC Module Registers ............................................................................................... 1880
32.5.1 Transmit Revision ID Register (TXREVID) ................................................................ 1883
32.5.2 Transmit Control Register (TXCONTROL)................................................................. 1883