Texas Instruments TMS570LC4357 - Page 28

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SPNU563A–March 2018
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Contents
32.5.3 Transmit Teardown Register (TXTEARDOWN)........................................................... 1884
32.5.4 Receive Revision ID Register (RXREVID)................................................................. 1884
32.5.5 Receive Control Register (RXCONTROL) ................................................................. 1885
32.5.6 Receive Teardown Register (RXTEARDOWN) ........................................................... 1885
32.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)................................... 1886
32.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................. 1887
32.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................... 1888
32.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ....................................... 1889
32.5.11 MAC Input Vector Register (MACINVECTOR) .......................................................... 1890
32.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................... 1891
32.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW).................................. 1892
32.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................ 1893
32.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) .............................................. 1894
32.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)........................................ 1895
32.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................... 1896
32.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED).................................. 1896
32.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)................................................ 1897
32.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................... 1897
32.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......... 1898
32.5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................. 1900
32.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................ 1901
32.5.24 Receive Maximum Length Register (RXMAXLEN)...................................................... 1901
32.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)................................................. 1902
32.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)................. 1902
32.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH) 1903
32.5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) ........ 1903
32.5.29 MAC Control Register (MACCONTROL) ................................................................. 1904
32.5.30 MAC Status Register (MACSTATUS)..................................................................... 1906
32.5.31 Emulation Control Register (EMCONTROL) ............................................................. 1908
32.5.32 FIFO Control Register (FIFOCONTROL)................................................................. 1908
32.5.33 MAC Configuration Register (MACCONFIG) ............................................................ 1909
32.5.34 Soft Reset Register (SOFTRESET)....................................................................... 1909
32.5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ..................................... 1910
32.5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)...................................... 1910
32.5.37 MAC Hash Address Register 1 (MACHASH1)........................................................... 1911
32.5.38 MAC Hash Address Register 2 (MACHASH2)........................................................... 1911
32.5.39 Back Off Test Register (BOFFTEST) ..................................................................... 1912
32.5.40 Transmit Pacing Algorithm Test Register (TPACETEST) .............................................. 1912
32.5.41 Receive Pause Timer Register (RXPAUSE)............................................................. 1913
32.5.42 Transmit Pause Timer Register (TXPAUSE) ............................................................ 1913
32.5.43 MAC Address Low Bytes Register (MACADDRLO) .................................................... 1914
32.5.44 MAC Address High Bytes Register (MACADDRHI)..................................................... 1915
32.5.45 MAC Index Register (MACINDEX) ........................................................................ 1915
32.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) .................. 1916
32.5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) .................. 1916
32.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)................................... 1917
32.5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP) ................................... 1917
32.5.50 Network Statistics Registers ............................................................................... 1918
33 Enhanced Capture (eCAP) Module .................................................................................... 1927
33.1 Introduction............................................................................................................... 1928
33.1.1 Features ........................................................................................................ 1928
33.1.2 Description ..................................................................................................... 1928
33.2 Basic Operation.......................................................................................................... 1929