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Module Operation
2163
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
37.2.7 GIO Function
Pins which are not used for RTP functionality can be used as normal GIO pins. If pins should be used in
functional mode or GIO mode, they can be programmed in the RTP pin control 0 register (RTPPC0). The
direction of the pins can be chosen in the RTP pin control 1 register (RTPPC1).
Module pins can have either an internal pullup or active pulldown that makes it possible to leave the pins
unconnected externally when configured as inputs. The pins can be programmed to have the active pull
capability by writing a 0 to the corresponding bit in the RTP pin control 7 register (RTPPC7). Writing a 1 to
the corresponding bit disables the active pull functionality of the pin. A pull up can be configured by writing
1 to the corresponding bit in the RTP pin control 8 register (RTPPC8). Writing 0 will activate the pulldown
capability. The pullup/pulldown is deactivated when a bidirectional pin is configured as an output. If the
pullup/down capability is disabled (RTPPC7) and the pull is configured as pulldown (RTPPC8), the input
buffer will be disabled.
The GIO pin can be configured to include an open drain functionality when they are configured as output
pins. This is done by writing a 1 into the corresponding bit of the RTP pin control 6 register (RTPPC6).
When the open drain functionality is enabled, a zero written to the data output register (RTPPC3) forces
the pin to a low output voltage (V
OL
or lower), whereas writing a 1 to the data output register (RTPPC3)
forces the pin to a high impedance state. The open drain functionality is disabled when the pin is
configured as an input pin.
37.3 RTP Control Registers
Table 37-7 lists the RTP module registers. The registers support 8-, 16-, and 32-bit writes. The base
address of the RTP module is FFFF FA00h.
Table 37-7. RTP Control Registers
Offset Acronym Register Description Section
00h RTPGLBCTRL RTP Global Control Register Section 37.3.1
04h RTPTRENA RTP Trace Enable Register Section 37.3.2
08h RTPGSR RTP Global Status Register Section 37.3.3
0Ch RTPRAM1REG1 RTP RAM 1 Trace Region 1 Register Section 37.3.4
10h RTPRAM1REG2 RTP RAM 1 Trace Region 2 Register Section 37.3.4
14h RTPRAM2REG1 RTP RAM 2 Trace Region 1 Register Section 37.3.5
18h RTPRAM2REG2 RTP RAM 2 Trace Region 2 Register Section 37.3.5
1Ch RTPRAM3REG1 RTP RAM 3 Trace Region 1 Register Section 37.3.6
20h RTPRAM3REG2 RTP RAM 3 Trace Region 2 Register Section 37.3.6
24h RTPPERREG1 RTP Peripheral Trace Region 1 Register Section 37.3.7
28h RTPPERREG2 RTP Peripheral Trace Region 2 Register Section 37.3.7
2Ch RTPDDMW RTP Direct Data Mode Write Register Section 37.3.8
34h RTPPC0 RTP Pin Control 0 Register Section 37.3.9
38h RTPPC1 RTP Pin Control 1 Register Section 37.3.10
3Ch RTPPC2 RTP Pin Control 2 Register Section 37.3.11
40h RTPPC3 RTP Pin Control 3 Register Section 37.3.12
44h RTPPC4 RTP Pin Control 4 Register Section 37.3.13
48h RTPPC5 RTP Pin Control 5 Register Section 37.3.14
4Ch RTPPC6 RTP Pin Control 6 Register Section 37.3.15
50h RTPPC7 RTP Pin Control 7 Register Section 37.3.16
54h RTPPC8 RTP Pin Control 8 Register Section 37.3.17
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