Revision History
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SPNU563A–March 2018
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Revision History
• Figure 20-107: Updated Read/Write value of TER_ERR bit to R/W1C-0....................................................... 786
• Figure 20-108: Updated Read/Write value of TERE bit to R/W1CP-0 .......................................................... 786
• Table 20-99: Updated Value column of TER_OFF bit. Added 21h-3Fh = Reserved.......................................... 787
• Table 20-103: Changed Description of TTYPE bit. (A request triggers) ........................................................ 790
• Chapter 21: External Memory Interface (EMIF) ................................................................................. 793
• Figure 21-1: Corrected pin names ................................................................................................... 795
• Figure 21-1: Deleted EMIF_RNW pin ............................................................................................... 795
• Table 21-3: Deleted EMIF_RNW pin ................................................................................................ 797
• Figure 21-18: Updated reset value of RR bit to 80h............................................................................... 831
• Figure 21-24: Changed bit 1 to LT_MASK_SET ................................................................................... 837
• Figure 21-25: Changed bit 1 to LT_MASK_CLR................................................................................... 838
• Figure 21-27: Corrected pin names.................................................................................................. 841
• Chapter 22: Analog To Digital Converter (ADC) Module ..................................................................... 848
• Figure 22-1: Corrected EXT_SEL and EXT_ENA signals ........................................................................ 850
• Figure 22-2: Corrected Event Trigger Generation signal ......................................................................... 851
• Figure 22-2: Corrected EXT_SEL and EXT_ENA signals ........................................................................ 851
• Figure 22-2: Deleted EXT_nENA signal............................................................................................. 851
• Section 22.1.1.3: Updated third and fifth sentences in third paragraph......................................................... 852
• Section 22.2.1.3: Added last sentence (reference) to fourth paragraph ........................................................ 854
• Figure 22-10: Corrected bit range of the EV_CURRENT_COUNT, EV_MAX_COUNT, G1_CURRENT_COUNT,
G1_MAX_COUNT, G2_CURRENT_COUNT, and G2_MAX_COUNT bits to 4-0 ............................................. 860
• Section 22.2.5.3: Corrected register names in first sentence. (ADMAGINTENASET and ADMAGINTENACLR)......... 870
• Table 22-11: Changed Description of FRZ_EV bit. (The Event Group conversion is kept frozen while the Group1 or
Group2 conversion is active,)......................................................................................................... 888
• Table 22-12: Changed Description of FRZ_G1 bit. (The Group1 conversion is kept frozen while the Event Group or
Group2 conversion is active,)......................................................................................................... 891
• Table 22-13: Changed Description of FRZ_G2 bit. (The Group2 conversion is kept frozen while the Event Group or
Group1 conversion is active,)......................................................................................................... 894
• Table 22-28: Changed Description for DMA_G2_END bit. Corrected group number to 2 ................................... 911
• Figure 22-53: Deleted Reserved bits. Changed EV_SEL bits to 31-0 .......................................................... 920
• Table 22-37: Deleted Reserved bits. Changed EV_SEL bits to 31-0 ........................................................... 920
• Figure 22-54: Deleted Reserved bits. Changed G1_SEL bits to 31-0 .......................................................... 921
• Table 22-38: Deleted Reserved bits. Changed G1_SEL bits to 31-0 ........................................................... 921
• Figure 22-55: Deleted Reserved bits. Changed G2_SEL bits to 31-0 .......................................................... 922
• Table 22-39: Deleted Reserved bits. Changed G2_SEL bits to 31-0 ........................................................... 922
• Table 22-42: Changed Description of LAST_CONV bit for Value = 1. (A level higher than or equal to the midpoint
reference voltage)...................................................................................................................... 924
• Chapter 23: High-End Timer (N2HET) Module .................................................................................. 953
• Section 23.2.5.4: Changed first sentence........................................................................................... 973
• Table 23-9: Changed Pull Control and Input Buffer = Enabled when device is under reset ................................. 985
• Section 23.2.9: Updated first paragraph ............................................................................................ 990
• Section 23.3.2: Added Hardware Angle Generator (HWAG) subsection. Subsequent figures and tables renumbered.. 995
• Figure 23-56: Changed format...................................................................................................... 1018
• Table 23-16: Updated Description of PPF and TO bits.......................................................................... 1018
• Table 23-17: Updated Description of LRPFC and HRPFC bits................................................................. 1020
• Table 23-26: Changed Description of HETPRY bit............................................................................... 1026
• Section 23.5: Added HWAG Registers section. Subsequent section, figures, and tables renumbered................... 1044
• Table 23-73: Added cross references to instruction descriptions .............................................................. 1060
• Table 23-73: Added OR instruction ................................................................................................ 1060
• Table 23-73: Corrected sub-opcodes for ADC, ADD, and XOR instructions ................................................. 1060
• Table 23-74: Added SUB to Set/Reset column for Zero flag (Z) ............................................................... 1061
• Section 23.6.3.8: Updated Description of CNT instruction. The data field [D31:7] is incremented unconditionally on each
execution of the instruction .......................................................................................................... 1086
• Table 23-87: Changed registers in Source and Destination(s) columns to register A, B, R, S, or T ...................... 1103
• Section 23.6.3.19: Updated Description of RCNT instruction. For example, choosing M = 100 allows the input period to be
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