Texas Instruments TMS570LC4357 - Page 60

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60
SPNU563A–March 2018
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List of Figures
27-75. IF3 Update Enable 12 Register (DCAN IF3UPD12) [offset = 160h].............................................. 1493
27-76. IF3 Update Enable 34 Register (DCAN IF3UPD34) [offset = 164h].............................................. 1493
27-77. IF3 Update Enable 56 Register (DCAN IF3UPD56) [offset = 168h].............................................. 1493
27-78. IF3 Update Enable 78 Register (DCAN IF3UPD78) [offset = 16Ch] ............................................. 1493
27-79. CAN TX IO Control Register (DCAN TIOC) [offset = 1E0h]....................................................... 1494
27-80. CAN RX IO Control Register (DCAN RIOC) [offset = 1E4h] ...................................................... 1495
28-1. SPI Functional Logic Diagram......................................................................................... 1501
28-2. MibSPI Functional Logic Diagram..................................................................................... 1502
28-3. DMA Channel and Request Line (Logical) Structure in Multi-buffer Mode ...................................... 1504
28-4. TG Interrupt Structure .................................................................................................. 1506
28-5. SPIFLG Interrupt Structure............................................................................................. 1506
28-6. SPI Three-Pin Operation .............................................................................................. 1507
28-7. Operation with SPICS .................................................................................................. 1508
28-8. Operation with SPIENA................................................................................................. 1509
28-9. SPI Five-Pin Option with SPIENA and SPICS ...................................................................... 1510
28-10. Format for Transmitting an 12-Bit Word.............................................................................. 1511
28-11. Format for Receiving an 10-Bit Word................................................................................. 1511
28-12. Clock Mode with Polarity = 0 and Phase = 0........................................................................ 1512
28-13. Clock Mode with Polarity = 0 and Phase = 1........................................................................ 1512
28-14. Clock Mode with Polarity = 1 and Phase = 0........................................................................ 1513
28-15. Clock Mode with Polarity = 1 and Phase = 1........................................................................ 1513
28-16. Five Bits per Character (5-Pin Option) ............................................................................... 1514
28-17. Example: t
C2TDELAY
= 8 VCLK Cycles................................................................................... 1515
28-18. Example: t
T2CDELAY
= 4 VCLK Cycles................................................................................... 1516
28-19. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 1516
28-20. Chip-Select-Active-to-ENA-Signal-Active-Timeout.................................................................. 1517
28-21. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) ...................................... 1518
28-22. Block Diagram Shift Register, MSB First............................................................................. 1520
28-23. Block Diagram Shift Register, LSB First ............................................................................. 1520
28-24. 2-data Line Mode (Phase 0, Polarity 0) .............................................................................. 1523
28-25. Two-Pin Parallel Mode Timing Diagram (Phase 0, Polarity 0) .................................................... 1523
28-26. 4-Data Line Mode (Phase 0, Polarity 0).............................................................................. 1524
28-27. 4 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 1524
28-28. 8-data Line Mode (Phase 0, Polarity 0) .............................................................................. 1525
28-29. 8 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 1526
28-30. Multi-buffer in Slave Mode ............................................................................................. 1527
28-31. I/O Paths During I/O Loopback Modes............................................................................... 1532
28-32. SPI Global Control Register 0 (SPIGCR0) [offset = 00h] .......................................................... 1536
28-33. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] .......................................................... 1537
28-34. SPI Interrupt Register (SPIINT0) [offset = 08h] ..................................................................... 1538
28-35. SPI Interrupt Level Register (SPILVL) [offset = 0Ch]............................................................... 1540
28-36. SPI Flag Register (SPIFLG) [offset = 10h] .......................................................................... 1541
28-37. SPI Pin Control Register 0 (SPIPC0) [offset = 14h] ................................................................ 1544
28-38. SPI Pin Control Register 1 (SPIPC1) [offset = 18h] ............................................................... 1545
28-39. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch]................................................................ 1547
28-40. SPI Pin Control Register 3 (SPIPC3) [offset = 20h] ............................................................... 1548
28-41. SPI Pin Control Register 4 (SPIPC4) [offset = 24h] ............................................................... 1549
28-42. SPI Pin Control Register 5 (SPIPC5) [offset = 28h] ............................................................... 1551
28-43. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] ............................................................... 1552