Texas Instruments TMS570LC4357 - Page 61

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SPNU563A–March 2018
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List of Figures
28-44. SPI Pin Control Register 7 (SPIPC7) [offset = 30h] ............................................................... 1554
28-45. SPI Pin Control Register 8 (SPIPC8) [offset = 34h] ............................................................... 1555
28-46. SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h] ........................................................... 1556
28-47. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]........................................................... 1557
28-48. SPI Receive Buffer Register (SPIBUF) [offset = 40h] .............................................................. 1560
28-49. SPI Emulation Register (SPIEMU) [offset = 44h] ................................................................... 1562
28-50. SPI Delay Register (SPIDELAY) [offset = 48h] ..................................................................... 1562
28-51. Example: t
C2TDELAY
= 8 VCLK Cycles.................................................................................... 1564
28-52. Example: t
T2CDELAY
= 4 VCLK Cycles.................................................................................... 1564
28-53. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 1564
28-54. Chip-Select-Active-to-ENA-Signal-Active-Timeout.................................................................. 1564
28-55. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] ........................................................ 1565
28-56. SPI Data Format Registers (SPIFMTn) [offset = 5Ch-50h]........................................................ 1566
28-57. Interrupt Vector 0 (NTVECT0) [offset = 60h] ........................................................................ 1568
28-58. Interrupt Vector 1 (INTVECT1) [offset = 64h]........................................................................ 1569
28-59. SPI Pin Control Register 9 (SPIPC9) [offset = 68h] ............................................................... 1571
28-60. Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch] ........................................... 1572
28-61. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]...................................................... 1575
28-62. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]..................................................... 1576
28-63. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h].................................................. 1577
28-64. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch] ........................................ 1578
28-65. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]...................................... 1579
28-66. Transfer Group Interrupt Flag Register (TGINTFLAG) [offset = 84h] ............................................ 1580
28-67. Tick Counter Operation................................................................................................. 1581
28-68. Tick Count Register (TICKCNT) [offset = 90h] ...................................................................... 1581
28-69. Last TG End Pointer (LTGPEND) [offset = 94h] .................................................................... 1582
28-70. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h] ................................................... 1583
28-71. DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h] ................................................ 1586
28-72. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h] ............................................................ 1588
28-73. DMA Large Count Register (DMACNTLEN) [offset = 118h]....................................................... 1589
28-74. Parity/ECC Control Register (PAR_ECC_CTRL) [offset = 120]................................................... 1590
28-75. Parity/ECC Status Register (PAR_ECC_STAT) [offset = 124].................................................... 1591
28-76. Uncorrectable Parity or Double-Bit ECC Error Address Register - RXRAM (UERRADDR1) [offset =
128h] ...................................................................................................................... 1592
28-77. Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM (UERRADDR0) [offset =
12Ch]...................................................................................................................... 1594
28-78. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]........................... 1595
28-79. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]........................................... 1596
28-80. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset =
138h] ...................................................................................................................... 1598
28-81. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset =
13Ch]...................................................................................................................... 1600
28-82. ECC Diagnostic Control Register (ECCDIAG_CTRL) [offset = 140h]............................................ 1601
28-83. ECC Diagnostic Status Register (ECCDIAG_STAT) [offset = 144h] ............................................. 1602
28-84. Single-Bit Error Address Register - RXRAM (SBERRADDR1) [offset = 148h] ................................. 1603
28-85. Single-Bit Error Address Register - TXRAM (SBERRADDR0) [offset = 14Ch] ................................. 1604
28-86. Multi-buffer RAM Configuration When Parity Check is Supported................................................ 1605
28-87. Multi-buffer RAM Configuration When ECC Check is Supported................................................. 1605
28-88. Multi-buffer RAM Transmit Data Register (TXRAM) [offset = Base + 000-1FFh]............................... 1607
28-89. Multi-buffer RAM Receive Buffer Register (RXRAM) [offset = RAM Base + 200-3FFh]....................... 1610