Texas Instruments TMS570LC4357 - Page 62

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SPNU563A–March 2018
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List of Figures
28-90. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Disabled or the Feature is Not Implemented ........................................................................ 1613
28-91. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Enabled................................................................................................................... 1614
28-92. Example of Memory-Mapped Parity Locations During Test Mode................................................ 1615
28-93. Example of ECC Bit Locations During Test Mode .................................................................. 1616
28-94. SPI/MibSPI Pins During Master Mode 3-Pin Configuration........................................................ 1617
28-95. SPI/MibSPI Pins During Master Mode 4-Pin with SPICS Configuation.......................................... 1617
28-96. SPI/MibSPI Pins During Master Mode in 4-Pin with SPIENA Configuration .................................... 1618
28-97. SPI/MibSPI Pins During Master/Slave Mode with 5-Pin Configuration .......................................... 1618
28-98. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration ......................................................... 1619
28-99. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration...................................... 1619
28-100. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single Slave) ................................... 1619
28-101. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single/Multi-Slave)............................. 1619
29-1. SCI Block Diagram...................................................................................................... 1625
29-2. SCI/LIN Block Diagram................................................................................................. 1626
29-3. Typical SCI Data Frame Formats ..................................................................................... 1627
29-4. Asynchronous Communication Bit Timing ........................................................................... 1628
29-5. Superfractional Divider Example ...................................................................................... 1630
29-6. Idle-Line Multiprocessor Communication Format ................................................................... 1632
29-7. Address-Bit Multiprocessor Communication Format................................................................ 1632
29-8. Receive Buffers.......................................................................................................... 1633
29-9. Transmit Buffers......................................................................................................... 1634
29-10. General Interrupt Scheme.............................................................................................. 1635
29-11. Interrupt Generation for Given Flags ................................................................................. 1636
29-12. LIN Protocol Message Frame Format: Master Header and Slave Response................................... 1643
29-13. Header 3 Fields: Synch Break, Synch, and ID ...................................................................... 1643
29-14. Response Format of LIN Message Frame........................................................................... 1644
29-15. Message Header in Terms of T
bit
...................................................................................... 1647
29-16. ID Field ................................................................................................................... 1647
29-17. Measurements for Synchronization ................................................................................... 1649
29-18. Synchronization Validation Process and Baud Rate Adjustment ................................................. 1650
29-19. Optional Embedded Checksum in Response for Extended Frames ............................................. 1651
29-20. Checksum Compare and Send for Extended Frames.............................................................. 1652
29-21. TXRX Error Detector.................................................................................................... 1654
29-22. Classic Checksum Generation at Transmitting Node .............................................................. 1655
29-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node ................................................. 1655
29-24. ID Reception, Filtering and Validation ................................................................................ 1657
29-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence .............................................. 1659
29-26. Wakeup Signal Generation ............................................................................................ 1663
29-27. GPIO Functionality ...................................................................................................... 1665
29-28. SCI Global Control Register 0 (SCIGCR0) (offset = 00) ........................................................... 1668
29-29. SCI Global Control Register 1 (SCIGCR1) (offset = 04h) ......................................................... 1669
29-30. SCI Global Control Register 2 (SCIGCR2) (offset = 08h) ......................................................... 1673
29-31. SCI Set Interrupt Register (SCISETINT) (offset = 0Ch)............................................................ 1675
29-32. SCI Clear Interrupt Register (SCICLEARINT) (offset = 10h) ...................................................... 1678
29-33. SCI Set Interrupt Level Register (SCISETINTLVL) (offset = 14h) ................................................ 1681
29-34. SCI Clear Interrupt Level Register (SCICLEARINTLVL) (offset = 18h).......................................... 1684
29-35. SCI Flags Register (SCIFLR) (offset = 1Ch) ........................................................................ 1687