Texas Instruments TMS570LC4357 - Page 63

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SPNU563A–March 2018
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List of Figures
29-36. SCI Interrupt Vector Offset 0 (SCIINTVECT0) (offset = 20h) ..................................................... 1694
29-37. SCI Interrupt Vector Offset 1 (SCIINTVECT1) (offset = 24h) ..................................................... 1694
29-38. SCI Format Control Register (SCIFORMAT) (offset = 28h) ....................................................... 1695
29-39. Baud Rate Selection Register (BRS) (offset = 2Ch)................................................................ 1696
29-40. Receiver Emulation Data Buffer (SCIED) (offset = 30h) ........................................................... 1698
29-41. Receiver Data Buffer (SCIRD) (offset = 34h)........................................................................ 1698
29-42. Transmit Data Buffer Register (SCITD) (offset = 38h) ............................................................. 1699
29-43. SCI Pin I/O Control Register 0 (SCIPIO0) (offset = 3Ch).......................................................... 1699
29-44. SCI Pin I/O Control Register 1 (SCIPIO1) (offset = 40h) .......................................................... 1700
29-45. SCI Pin I/O Control Register 2 (SCIPIO2) (offset = 44h) .......................................................... 1701
29-46. SCI Pin I/O Control Register 3 (SCIPIO3) (offset = 48h) .......................................................... 1702
29-47. SCI Pin I/O Control Register 4 (SCIPIO4) (offset = 4Ch).......................................................... 1703
29-48. SCI Pin I/O Control Register 5 (SCIPIO5) (offset = 50h) .......................................................... 1704
29-49. SCI Pin I/O Control Register 6 (SCIPIO6) (offset = 54h) .......................................................... 1705
29-50. SCI Pin I/O Control Register 7 (SCIPIO7) (offset = 58h) .......................................................... 1706
29-51. SCI Pin I/O Control Register 8 (SCIPIO8) (offset = 5Ch).......................................................... 1707
29-52. LIN Compare Register (LINCOMPARE) (offset = 60h) ............................................................ 1708
29-53. LIN Receive Buffer 0 Register (LINRD0) (offset = 64h)............................................................ 1709
29-54. LIN Receive Buffer 1 Register (RD1) (offset = 68h) ................................................................ 1710
29-55. LIN Mask Register (LINMASK) (offset = 6Ch)....................................................................... 1711
29-56. LIN Identification Register (LINID) (offset = 70h) ................................................................... 1712
29-57. LIN Transmit Buffer 0 Register (LINTD0) (offset = 74h) ........................................................... 1713
29-58. LIN Transmit Buffer 1 Register (LINTD1) (offset = 78h) ........................................................... 1713
29-59. Maximum Baud Rate Selection Register (MBRS) (offset = 7Ch) ................................................. 1714
29-60. Input/Output Error Enable Register (IODFTCTRL) (offset = 90h) ................................................ 1715
30-1. Detailed SCI Block Diagram ........................................................................................... 1719
30-2. Typical SCI Data Frame Formats ..................................................................................... 1720
30-3. Asynchronous Communication Bit Timing ........................................................................... 1721
30-4. Idle-Line Multiprocessor Communication Format ................................................................... 1723
30-5. Address-Bit Multiprocessor Communication Format................................................................ 1724
30-6. General Interrupt Scheme.............................................................................................. 1725
30-7. Interrupt Generation for Given Flags ................................................................................. 1726
30-8. SCI Global Control Register 0 (SCIGCR0) [offset = 00] ........................................................... 1734
30-9. SCI Global Control Register 1 (SCIGCR1) [offset = 04h].......................................................... 1735
30-10. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................ 1738
30-11. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ...................................................... 1740
30-12. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h] ................................................ 1742
30-13. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] .......................................... 1743
30-14. SCI Flags Register (SCIFLR) [offset = 1Ch]......................................................................... 1745
30-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h]...................................................... 1749
30-16. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h]...................................................... 1749
30-17. SCI Format Control Register (SCIFORMAT) [offset = 28h] ....................................................... 1750
30-18. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 1751
30-19. Receiver Emulation Data Buffer (SCIED) [offset = 30h] ........................................................... 1752
30-20. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 1752
30-21. Transmit Data Buffer Register (SCITD) [offset = 38h].............................................................. 1753
30-22. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch] ......................................................... 1753
30-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h]........................................................... 1754
30-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] .......................................................... 1755