www.ti.com
64
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
List of Figures
30-25. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h]........................................................... 1756
30-26. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] ......................................................... 1757
30-27. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h]........................................................... 1758
30-28. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] .......................................................... 1759
30-29. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h]........................................................... 1760
30-30. SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] ......................................................... 1760
30-31. Input/Output Error Enable Register (IODFTCTRL) [offset = 90h]................................................. 1761
30-32. GPIO Functionality ...................................................................................................... 1763
31-1. Multiple I2C Modules Connection Diagram .......................................................................... 1766
31-2. Simple I2C Block Diagram ............................................................................................. 1768
31-3. Clocking Diagram for the I2C Module ................................................................................ 1769
31-4. Bit Transfer on the I2C Bus............................................................................................ 1770
31-5. I2C Module START and STOP Conditions .......................................................................... 1771
31-6. I2C Module Data Transfer.............................................................................................. 1771
31-7. I2C Module 7-Bit Addressing Format................................................................................. 1772
31-8. I2C Module 10-bit Addressing Format................................................................................ 1772
31-9. I2C Module 7-Bit Addressing Format with Repeated START ..................................................... 1772
31-10. I2C Module in Free Data Format...................................................................................... 1773
31-11. Arbitration Procedure Between Two Master Transmitters ......................................................... 1776
31-12. Synchronization of Two I2C Clock Generators During Arbitration................................................ 1777
31-13. I2C Own Address Manager Register (I2COAR) [offset = 00] ..................................................... 1782
31-14. I2C Interrupt Mask Register (I2CIMR) [offset = 04h] ............................................................... 1783
31-15. I2C Status Register (I2CSR) [offset = 08h] .......................................................................... 1784
31-16. I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch] .......................................................... 1787
31-17. I2C Clock Control High Register (I2CCKH) [offset = 10h] ......................................................... 1787
31-18. I2C Data Count Register (I2CCNT) [offset = 14h] .................................................................. 1788
31-19. I2C Data Receive Register (I2CDRR) [offset = 18h] ............................................................... 1788
31-20. I2C Slave Address Register (I2CSAR) [offset = 1Ch] .............................................................. 1789
31-21. I2C Data Transmit Register (I2CDXR) [offset = 20h]............................................................... 1789
31-22. I2C Mode Register (I2CMDR) [offset = 24h]......................................................................... 1790
31-23. Typical Timing Diagram of Repeat Mode ............................................................................ 1792
31-24. I2C Interrupt Vector Register (I2CIVR) [offset = 28h] .............................................................. 1793
31-25. I2C Extended Mode Register (I2CEMDR) [offset = 2Ch] .......................................................... 1794
31-26. I2C Prescale Register (I2CPSC) [offset = 30h] ..................................................................... 1794
31-27. I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] ............................................................. 1795
31-28. I2C Peripheral ID Register 2 (I2CPID2) [offset = 38h] ............................................................. 1795
31-29. I2C DMA Control Register (I2CDMACR) [offset = 3Ch]............................................................ 1796
31-30. I2C Pin Function Register (I2CPFNC) [offset = 48h] ............................................................... 1796
31-31. I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] ............................................................... 1797
31-32. I2C Data Input Register (I2CDIN) [offset = 50h] .................................................................... 1797
31-33. I2C Data Output Register (I2CDOUT) [offset 0x54] ................................................................ 1798
31-34. I2C Data Set Register (I2CDSET) [offset = 58h].................................................................... 1798
31-35. I2C Data Clear Register (I2CDCLR) [offset = 5Ch]................................................................. 1799
31-36. I2C Pin Open Drain Register (I2CPDR) [offset = 60h] ............................................................. 1799
31-37. I2C Pull Disable Register (I2CPDIS) [offset = 64h]................................................................. 1800
31-38. I2C Pull Select Register (I2CPSEL) [offset = 68h].................................................................. 1800
31-39. I2C Pins Slew Rate Select Register (I2CSRS) [offset = 6Ch]..................................................... 1801
31-40. Difference between Normal Operation and Backward Compatibility Mode...................................... 1802
32-1. EMAC and MDIO Block Diagram ..................................................................................... 1805
To Next Page
Loading...
