Texas Instruments TMS570LC4357 - Page 65

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65
SPNU563A–March 2018
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List of Figures
32-2. Ethernet Configuration—MII Connections ........................................................................... 1807
32-3. Ethernet Configuration—RMII Connections.......................................................................... 1809
32-4. Ethernet Frame Format................................................................................................. 1811
32-5. Basic Descriptor Format................................................................................................ 1812
32-6. Typical Descriptor Linked List ......................................................................................... 1813
32-7. Transmit Packet Add Flow Chart...................................................................................... 1815
32-8. Generate Transmit Packet Flow Chart ............................................................................... 1816
32-9. Transmit Queue Interrupt Processing Flow Chart .................................................................. 1817
32-10. Transmit Buffer Descriptor Format.................................................................................... 1819
32-11. Receive Buffer Descriptor Format..................................................................................... 1823
32-12. EMAC Control Module Block Diagram ............................................................................... 1827
32-13. MDIO Module Block Diagram.......................................................................................... 1828
32-14. EMAC Module Block Diagram......................................................................................... 1833
32-15. EMAC Control Module Revision ID Register (REVID) (offset = 00h)............................................. 1855
32-16. EMAC Control Module Software Reset Register (SOFTRESET) (offset = 04h) ................................ 1855
32-17. EMAC Control Module Interrupt Control Register (INTCONTROL) (offset = 0Ch) ............................. 1856
32-18. EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) (offset = 10h) .. 1857
32-19. EMAC Control Module Receive Interrupt Enable Register (C0RXEN) (offset = 14h).......................... 1858
32-20. EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) (offset = 18h) ......................... 1859
32-21. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) (offset = 1Ch) ............... 1860
32-22. EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) (offset = 40h) 1861
32-23. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) (offset = 44h) ....................... 1862
32-24. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) (offset = 48h) ....................... 1863
32-25. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) (offset = 4Ch)............. 1864
32-26. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) (offset = 70h)............ 1865
32-27. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) (offset = 74h) ........... 1866
32-28. MDIO Revision ID Register (REVID) (offset = 00h) ................................................................ 1867
32-29. MDIO Control Register (CONTROL) (offset = 04h)................................................................. 1868
32-30. PHY Acknowledge Status Register (ALIVE) (offset = 08h)........................................................ 1869
32-31. PHY Link Status Register (LINK) (offset = 0Ch) .................................................................... 1869
32-32. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) (offset = 10h).................... 1870
32-33. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) (offset = 14h) .................. 1871
32-34. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) (offset = 20h)........... 1872
32-35. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) (offset = 24h) ......... 1873
32-36. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) (offset = 28h)........ 1874
32-37. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) (offset = 2Ch) . 1875
32-38. MDIO User Access Register 0 (USERACCESS0) (offset = 80h) ................................................. 1876
32-39. MDIO User PHY Select Register 0 (USERPHYSEL0) (offset = 84h) ............................................ 1877
32-40. MDIO User Access Register 1 (USERACCESS1) (offset = 88h) ................................................. 1878
32-41. MDIO User PHY Select Register 1 (USERPHYSEL1) (offset = 8Ch)............................................ 1879
32-42. Transmit Revision ID Register (TXREVID) (offset = 00h).......................................................... 1883
32-43. Transmit Control Register (TXCONTROL) (offset = 04h).......................................................... 1883
32-44. Transmit Teardown Register (TXTEARDOWN) (offset = 08h) .................................................... 1884
32-45. Receive Revision ID Register (RXREVID) (offset = 10h) .......................................................... 1884
32-46. Receive Control Register (RXCONTROL) (offset = 14h) .......................................................... 1885
32-47. Receive Teardown Register (RXTEARDOWN) (offset = 18h) .................................................... 1885
32-48. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) (offset = 80h) ............................ 1886
32-49. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) (offset = 84h) .......................... 1887
32-50. Transmit Interrupt Mask Set Register (TXINTMASKSET) (offset = 88h) ........................................ 1888