Texas Instruments TMS570LC4357 - Page 66

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SPNU563A–March 2018
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List of Figures
32-51. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) (offset = 8Ch).................................. 1889
32-52. MAC Input Vector Register (MACINVECTOR) (offset = 90h) ..................................................... 1890
32-53. MAC End Of Interrupt Vector Register (MACEOIVECTOR) (offset = 94h)...................................... 1891
32-54. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) (offset = A0h) ............................ 1892
32-55. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) (offset = A4h)........................... 1893
32-56. Receive Interrupt Mask Set Register (RXINTMASKSET) (offset = A8h) ........................................ 1894
32-57. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) (offset = ACh).................................. 1895
32-58. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) (offset = B0h).............................. 1896
32-59. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) (offset = B4h) ............................ 1896
32-60. MAC Interrupt Mask Set Register (MACINTMASKSET) (offset = B8h).......................................... 1897
32-61. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) (offset = BCh) ................................... 1897
32-62. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) (offset = 100h) .. 1898
32-63. Receive Unicast Enable Set Register (RXUNICASTSET) (offset = 104h) ...................................... 1900
32-64. Receive Unicast Clear Register (RXUNICASTCLEAR) (offset = 108h).......................................... 1901
32-65. Receive Maximum Length Register (RXMAXLEN) (offset = 10Ch) .............................................. 1901
32-66. Receive Buffer Offset Register (RXBUFFEROFFSET) (offset = 110h) .......................................... 1902
32-67. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) (offset = 114h).......... 1902
32-68. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) (offset = 120h-13Ch).......... 1903
32-69. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) (offset = 140h-15Ch) ................. 1903
32-70. MAC Control Register (MACCONTROL) (offset = 160h) .......................................................... 1904
32-71. MAC Status Register (MACSTATUS) (offset = 164h).............................................................. 1906
32-72. Emulation Control Register (EMCONTROL) (offset = 168h) ...................................................... 1908
32-73. FIFO Control Register (FIFOCONTROL) (offset = 16Ch) ......................................................... 1908
32-74. MAC Configuration Register (MACCONFIG) (offset = 170h)...................................................... 1909
32-75. Soft Reset Register (SOFTRESET) (offset = 174h) ................................................................ 1909
32-76. MAC Source Address Low Bytes Register (MACSRCADDRLO) (offset = 1D0h) .............................. 1910
32-77. MAC Source Address High Bytes Register (MACSRCADDRHI) (offset = 1D4h) .............................. 1910
32-78. MAC Hash Address Register 1 (MACHASH1) (offset = 1D8h) ................................................... 1911
32-79. MAC Hash Address Register 2 (MACHASH2) (offset = 1DCh)................................................... 1911
32-80. Back Off Random Number Generator Test Register (BOFFTEST) (offset = 1E0h)............................ 1912
32-81. Transmit Pacing Algorithm Test Register (TPACETEST) (offset = 1E4h)....................................... 1912
32-82. Receive Pause Timer Register (RXPAUSE) (offset = 1E8h)...................................................... 1913
32-83. Transmit Pause Timer Register (TXPAUSE) (offset = 1ECh)..................................................... 1913
32-84. MAC Address Low Bytes Register (MACADDRLO) (offset = 500h).............................................. 1914
32-85. MAC Address High Bytes Register (MACADDRHI) (offset = 504h) .............................................. 1915
32-86. MAC Index Register (MACINDEX) (offset = 508h) ................................................................. 1915
32-87. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) (offset = 600h-61Ch)............... 1916
32-88. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) (offset = 620h-63Ch) ............... 1916
32-89. Transmit Channel n Completion Pointer Register (TXnCP) (offset = 640h-65Ch) ............................. 1917
32-90. Receive Channel n Completion Pointer Register (RXnCP) (offset = 660h-67Ch).............................. 1917
32-91. Statistics Register ....................................................................................................... 1918
33-1. Capture and APWM Modes of Operation ............................................................................ 1929
33-2. Capture Function Diagram ............................................................................................. 1930
33-3. Event Prescale Control ................................................................................................. 1931
33-4. Prescale Function Waveforms......................................................................................... 1931
33-5. Continuous/One-shot Block............................................................................................ 1932
33-6. Counter and Synchronization Block .................................................................................. 1933
33-7. Interrupts in eCAP Module............................................................................................. 1934
33-8. PWM Waveform Details of APWM Mode Operation................................................................ 1935